ARM – WikiChip Fuse

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor 5 nm, Alibaba, Apsara Conference 2021, ARM, ARMv9, Panjiu, RISC-V, T-Head, TSMC, Xuantie, Yitian 710

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

Data Processing Unit

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor 5 nm, ARM, ARMv9, Data Processing Unit (DPU), Marvell, Neoverse N2, Octeon

Marvell launches the OCTEON 10 DPU series. Fabricated on a 5 nm process, these chips integrate Neoverse N2 cores, AI acceleration, vector packet processing acceleration, a 1 terabit switch, and the latest DDR5 and PCIe 5.0 I/O interfaces

Architectures

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor ARM, ARMv9, ARMv9.2, Confidential Compute Architecture (CCA), confidential computing, Dynamic TrustZone, Realm Management Extension (RME), secure enclave, TrustZone

Arm introduces its Confidential Compute Architecture (CCA) which provides a mechanism for Realms, secure enclaves that may be used by any application in order to protect data in use from everything else on the system.

IEDM 2020 Interconnects Packaging Subscriber Only Content

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Interconnects Network-on-Chip

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, cache coherency, CI-700, CMN-700, CoreLink, interconnects, Memory Tagging Extension (MTE), mesh interconnect, NI-700

Arm is introducing a new cache-coherent and SoC-level interconnects, the CoreLink CI-700 & NI-700.

Architectures Interconnects Mobile Processors

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, DSU-110, Memory Tagging Extension (MTE)

Arm introduces its new DynamIQ Share Unit 110 for new Armv9 CPUs

Architectures Embedded Processors Mobile Processors

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-X, Cortex-X2, Scalable Vector Extension 2 (SVE2)

Arm launches the Cortex-X2, second-generation Cortex-X, and their new flagship performance Armv9 big core.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

May 25, 2021May 26, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A510, Scalable Vector Extension 2 (SVE2)

Arm introduces their new Armv9 little core, the Cortex-A510 with significant PPA improvements.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Big Core: Cortex-A710

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A710, Scalable Vector Extension 2 (SVE2)

Arm unveils their newest Armv9 big core, the Cortex-A710.

Architectures Interconnects

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor ARM, CMN-600, CMN-700, DDR5, mesh interconnect, neoverse, Neoverse N, Neoverse V, PCIe 5.0

Arm’s CMN-700 is the company’s latest high-performance cache-coherent mesh interconnect for the server market, enabling SoC designs with twice as many cores, as much as half a GiB of cache, dozens of memory controllers, and support dozens of cache-coherent accelerators, chiplets, and processors.

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