Skip to content
Sunday, March 26, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

10 nm

Architectures Desktop Processors 

Intel Launches 12th Gen Core Desktop Alder Lake Processors

October 27, 2021November 3, 2021 David Schor 10 nm, 12 Generation Core, Alder Lake, Core i5, Core i7, Core i9, Intel, Intel 7

Intel launches 12th Gen Core desktop processors based on the Alder Lake microarchitecture.

Read more
Foundries IEDM 2020 Process Technologies Subscriber Only Content 

Intel Talks 10nm DTCO, EUV Benefits

June 22, 2021August 2, 2021 David Schor 10 nm, 5 nm, 7 nm, EUV, IEDM, IEDM 2020, Intel, subscriber only (general)

Intel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.

Read more
Packaging Power Management Subscriber Only Content 

The Magnets Under the Icy Lake

May 23, 2021July 8, 2021 David Schor 10 nm, Fully Integrated Voltage Regulator (FIVR), Ice Lake, subscriber only (general)

The magnets under the icy lake

Read more
Foundries 

Q1 2021 Foundry Update: Spending Bonanza

May 18, 2021May 23, 2021 David Schor 10 nm, 3 nm, 5 nm, 7 nm, FinFET, GAA, Intel, Samsung, SMIC, TSMC

A look at the current state of leading-edge foundries for the first quarter of 2021.

Read more
Embedded Processors Mobile Processors 

Intel Pushes Out Flagship Premium Tiger Lake Mobile Chips

May 13, 2021May 23, 2021 David Schor 10 nm, 11 Generation Core, Core i5, Core i7, Core i9, Intel, Tiger Lake, Willow Cove

In rolls out flagship premium performance 11th Generation Core Tiger Lake-based mobile processors with eight cores.

Read more
Mobile Processors 

Intel Launches Lakefield: An Experiment With Multiple New Technologies

June 15, 2020May 23, 2021 David Schor 10 nm, 22 nm, 22FFL, 3D packaging, Core i3, Core i5, Foveros, Intel, Lakefield, Sunny Cove, Tremont

Intel launches Lakefield, a 3D SoC with a new form factor for ultra-mobile devices. This microprocessor allows the chip giant to dabble with a number of new complementary technologies that could potentially find broader uses in the future.

Read more
Architectures Hot Chips 31 IEDM 2019 ISSCC 2020 

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020May 25, 2021 David Schor 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Read more
IEDM 2019 Process Technologies Roadmaps 

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

December 10, 2019May 25, 2021 David Schor 1.4 nm, 10 nm, 10nm, 2 nm, 3 nm, 5 nm, 7 nm, Intel

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

Read more
Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

November 17, 2019May 25, 2021 David Schor 10 nm, 7 nm, Aurora, Intel, Sapphire Rapids, Supercomputer, Supercomputers, x86, Xe

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

Read more
Process Technologies VLSI 2018 

VLSI 2018: Samsung’s 11nm nodelet, 11LPP

June 30, 2018May 25, 2021 David Schor 10 nm, 11 nm, 11LPP, 14 nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 11nm 11LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

Read more
  • ← Previous

Top Six Articles

  • A Look At Intel 4 Process Technology
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Arm Introduces The Cortex-A715
  • N3E Replaces N3; Comes In Many Flavors
  • Arm Introduces Its Confidential Compute Architecture
  • Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance

Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance

May 26, 2019May 25, 2021 David Schor
IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology

IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology

February 3, 2018May 25, 2021 David Schor
Intel silently launches Knights Mill

Intel silently launches Knights Mill

December 18, 2017May 25, 2021 David Schor
Intel Announces Keem Bay: 3rd Generation Movidius VPU

Intel Announces Keem Bay: 3rd Generation Movidius VPU

November 12, 2019May 25, 2021 David Schor
Arm Introduces The Cortex-A715

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

July 20, 2019May 25, 2021 David Schor
Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

May 25, 2021May 26, 2021 David Schor
AMD Launches Ryzen PRO 3000 Series

AMD Launches Ryzen PRO 3000 Series

October 3, 2019May 25, 2021 David Schor
Ampere Ships First Gen ARM Server Processors

Ampere Ships First Gen ARM Server Processors

September 19, 2018May 25, 2021 David Schor
Intel Updates Apollo Lake: More LPC Reliability Issues

Intel Updates Apollo Lake: More LPC Reliability Issues

September 9, 2019May 25, 2021 David Schor
Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping

Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping

May 28, 2019May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.