Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer
[Subscriber Content] Inside Preferred Networks’ AI processor and the world’s most power-efficient supercomputer it powers.
Read more[Subscriber Content] Inside Preferred Networks’ AI processor and the world’s most power-efficient supercomputer it powers.
Read moreTSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.
Read moreIntel unveils the Foveros Omni and Foveros Direct packaging technologies; which will be leveraging multiple base dies and hybrid bonding
Read moreWith hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.
Read moreAMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.
Read moreThe magnets under the icy lake
Read moreA look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.
Read moreRanovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.
Read moreTSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.
Read moreIntegrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.
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