Packaging

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

David SchorFoundries, Interconnects, Packaging, Process TechnologiesMay 11, 2019 Tagged 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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