Packaging

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

FPGAs Packaging November 7, 2019 0

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

Architectures Interconnects Packaging Process Technologies September 21, 2019 1

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

Packaging Process Technologies SEMICON West 2019 VLSI 2019 July 28, 2019 3

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects

Interconnects Packaging July 9, 2019 2

Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

Interconnects Packaging Server Processors VLSI 2019 June 22, 2019 0

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

Foundries Interconnects Packaging Process Technologies May 11, 2019 0

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

Interconnects Packaging Process Technologies December 22, 2018 1

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.