Packaging

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

Pages: 1 2

Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem

David SchorARM TechCon 2018, Foundries, Packaging, Process TechnologiesOctober 28, 2018 Tagged 2.5D packaging, 3D packaging, 3GAAE, 3GAAP, 3GAE, 3nm, 4LPE, 4LPP, 5LPE, 5nm, 7LPP, 7nm, EUV, Packaging, Samsung

Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.

Pages: 1 2

Hot Chips 30: Intel Kaby Lake G

David SchorCircuit Design, Hot Chips 30, PackagingSeptember 9, 2018 Tagged 14nm, 2.5D packaging, 3D packaging, AMD, CPU, EMIB, GPU, Intel, Kaby Lake, Kaby Lake G, multi-chip package, Radeon Vega, x86

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

Pages: 1 2