Packaging

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

Packaging Power Management Subscriber Only Content

The Magnets Under the Icy Lake

May 23, 2021May 23, 2021 David Schor 10 nm, Fully Integrated Voltage Regulator (FIVR), Ice Lake, subscriber only (general)

The magnets under the icy lake

Interconnects Packaging Process Technologies

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020May 23, 2021 David Schor 2.5D packaging, 3D packaging, Co-EMIB, EMIB, Foveros, Intel

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Interconnects Packaging Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020May 25, 2021 David Schor co-packaged optics (CPO), co-packaging, Ranovus, Ranovus Odin, silicon photonics

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020May 25, 2021 David Schor 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

Architectures Circuit Design Hot Chips 31 Interconnects Packaging

Ayar Labs Realizes Co-Packaged Silicon Photonics

January 19, 2020May 25, 2021 David Schor 45 nm, 45RFSOI, Ayar Labs, chiplet, GlobalFoundries, GlobalFoundries Technology Conference (GTC), Hot Chips, Hot Chips 31, Intel, multi-chip package, Photonics, silicon photonics, Stratix 10, TeraPHY

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

Interconnects Packaging

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020May 25, 2021 David Schor 2.5D packaging, Advanced Interface Bus (AIB), chiplet, EMIB, interposer, OCP Accelerator Module (OAM), OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

Architectures Hot Chips 31 Interconnects Neural Processors Packaging

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

November 16, 2019May 25, 2021 David Schor 16nm, AI, Cerebras, Hot Chips, Hot Chips 31, neural processors, training, Wafer-Scale Engine (WSE)

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

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