Packaging

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

Interconnects Packaging Process Technologies May 17, 2020 3

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

Interconnects Packaging Silicon Photonics April 11, 2020 0

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

Interconnects Packaging Process Technologies March 3, 2020 0

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

Ayar Labs Realizes Co-Packaged Silicon Photonics

Architectures Circuit Design Hot Chips 31 Interconnects Packaging January 19, 2020 0

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

OCP Makes a Push for an Open Chiplet Marketplace

Interconnects Packaging January 4, 2020 0

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

TSMC Digs Trenches In Search Of Higher Performance

IEDM 2019 Interconnects Packaging Process Technologies December 14, 2019 0

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

Architectures Hot Chips 31 Interconnects Neural Processors Packaging November 16, 2019 0

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

FPGAs Packaging November 7, 2019 0

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

Architectures Interconnects Packaging Process Technologies September 21, 2019 2

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

Packaging Process Technologies SEMICON West 2019 VLSI 2019 July 28, 2019 3

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.