Packaging

A Look At AMD’s 3D-Stacked V-Cache

December 27, 2022December 27, 2022 David Schor 3D V-Cache, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, subscriber only (general), System on Integrated Chips (SoIC)

[Subscription] A technical look at AMD’s 3D-Stacked V-Cache

Packaging Subscriber Only Content

TSMC Demos SoIC_H for High-Bandwidth HPC Applications

October 4, 2022October 4, 2022 David Schor 2.5D packaging, 3D packaging, HPC, hybrid bonding, SoIC, SoIC_H, SRAM cube, subscriber only (general), TSMC

[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.

Architectures Neural Processors Packaging Subscriber Only Content

Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer

September 20, 2021September 20, 2021 David Schor neural processors, Preferred Networks, subscriber only (general), Supercomputers

[Subscriber Content] Inside Preferred Networks’ AI processor and the world’s most power-efficient supercomputer it powers.

Packaging Subscriber Only Content

5th Gen CoWoS-S Extends 3 Reticle Size

August 2, 2021August 2, 2021 David Schor 2.5D packaging, CoWoS, HBM2e, HBM3, interposer, subscriber only (general), TSMC

TSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.

Packaging Roadmaps

Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding

July 26, 2021July 26, 2021 David Schor 3D packaging, die stacking, EMIB, Foveros, Intel

Intel unveils the Foveros Omni and Foveros Direct packaging technologies; which will be leveraging multiple base dies and hybrid bonding

IEDM 2020 Interconnects Packaging Subscriber Only Content

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

Packaging Power Management Subscriber Only Content

The Magnets Under the Icy Lake

May 23, 2021July 8, 2021 David Schor 10 nm, Fully Integrated Voltage Regulator (FIVR), Ice Lake, subscriber only (general)

The magnets under the icy lake

Interconnects Packaging Process Technologies

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020May 23, 2021 David Schor 2.5D packaging, 3D packaging, Co-EMIB, EMIB, Foveros, Intel

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Interconnects Packaging Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020May 25, 2021 David Schor co-packaged optics (CPO), co-packaging, Ranovus, Ranovus Odin, silicon photonics

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

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