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  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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subscriber only (general)

Circuit Design Desktop Processors Interconnects Packaging Server Processors Subscriber Only Content 

A Look At AMD’s 3D-Stacked V-Cache

December 27, 2022December 27, 2022 David Schor 3D V-Cache, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, subscriber only (general), System on Integrated Chips (SoIC)

[Subscription] A technical look at AMD’s 3D-Stacked V-Cache

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Packaging Subscriber Only Content 

TSMC Demos SoIC_H for High-Bandwidth HPC Applications

October 4, 2022October 4, 2022 David Schor 2.5D packaging, 3D packaging, HPC, hybrid bonding, SoIC, SoIC_H, SRAM cube, subscriber only (general), TSMC

[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.

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Architectures Neural Processors Subscriber Only Content 

The NPU Inside Every Intel PC

September 30, 2022September 30, 2022 David Schor Intel, subscriber only (general)

[Subscription] A look at the neural processor inside every Intel processor.

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Foundries Roadmaps Subscriber Only Content 

Samsung Foundry On EUV, Pellicles, Capacity, and Yield

July 25, 2022July 25, 2022 David Schor 4 nm, 5 nm, Extreme Ultraviolet (EUV) Lithography, Samsung, Samsung Foundry, subscriber only (general)

Samsung Foundry talks about EUV, wafer capacity and mid-term plans,pPellicles, and advanced node yield.

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Foundries IEDM 2021 Process Technologies Subscriber Only Content 

A Look At Samsung’s 4LPE Process

June 26, 2022June 26, 2022 David Schor 4 nm, 4LPE, 4LPP, FinFET, Samsung, Samsung Foundry, subscriber only (general)

A look at Samsung’s last leading-edge FinFET process node, 4nm 4LPE.

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Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor 14 nm, 14LPP, 17 nm, 17LPV, 28 nm, 28LPP, Intel, Intel Foundry Services (IFS), Samsung, Samsung Foundry, subscriber only (general)

Samsung follows Intel 16 with a low-cost high-performance, 17-nanometer, 17LPV node.

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Foundries Process Technologies Roadmaps Subscriber Only Content 

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

November 20, 2021November 20, 2021 David Schor ASML, Extreme Ultraviolet (EUV) Lithography, High-NA, subscriber only (general)

A look at the current state of EUV machines, the new NXE:3600D, and EUV pellicle readiness and industrialization.

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Architectures Neural Processors Packaging Subscriber Only Content 

Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer

September 20, 2021September 20, 2021 David Schor neural processors, Preferred Networks, subscriber only (general), Supercomputers

[Subscriber Content] Inside Preferred Networks’ AI processor and the world’s most power-efficient supercomputer it powers.

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Architectures Data Processing Unit Subscriber Only Content 

YouTube Accelerates Transcoding

August 21, 2021August 21, 2021 David Schor accelerator, ASPLOS 2021, google, H.264, subscriber only (general), video acceleration, Video Coding Unit (VCU), VP9, YouTube

Google accelerates YouTube and other video services with custom silicon.

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Silicon Photonics Subscriber Only Content VLSI 2021 

Photonics Chiplet Inches Towards Production

August 16, 2021August 22, 2021 David Schor 45 nm, 45RFSOI, Ayar Labs, chiplet, silicon photonics, subscriber only (general), TeraPHY, VLSI 2021

[Subscriber Content] Ayar Labs photonics chiplet inches towards production readiness

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  • ← Previous

Top Six Articles

  • A Look At Intel 4 Process Technology
  • A Look At AMD’s 3D-Stacked V-Cache
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

December 12, 2019May 25, 2021 David Schor
ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest

ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest

June 16, 2018May 25, 2021 David Schor
Intel Cascade Lake Brings Hardware Mitigations, AI Acceleration, SCM Support

Intel Cascade Lake Brings Hardware Mitigations, AI Acceleration, SCM Support

November 11, 2018May 25, 2021 David Schor
Eni fires up its supercomputer, breaks into the TOP500’s top ten

Eni fires up its supercomputer, breaks into the TOP500’s top ten

January 19, 2018May 25, 2021 David Schor
Intel axes Knights Hill, plans a new microarchitecture for exascale

Intel axes Knights Hill, plans a new microarchitecture for exascale

November 14, 2017May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

November 7, 2019May 25, 2021 David Schor
Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

October 20, 2019May 25, 2021 David Schor
The 2,048-core PEZY-SC2 sets a Green500 record

The 2,048-core PEZY-SC2 sets a Green500 record

November 1, 2017May 25, 2021 David Schor
Intel Announces Keem Bay: 3rd Generation Movidius VPU

Intel Announces Keem Bay: 3rd Generation Movidius VPU

November 12, 2019May 25, 2021 David Schor
IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

February 17, 2018May 25, 2021 David Schor
Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

October 14, 2018May 25, 2021 David Schor
BrainChip Discloses Akida, A Neuromorphic SoC

BrainChip Discloses Akida, A Neuromorphic SoC

September 28, 2018May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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