subscriber only (general)

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Packaging Power Management Subscriber Only Content

The Magnets Under the Icy Lake

May 23, 2021May 23, 2021 David Schor 10 nm, Fully Integrated Voltage Regulator (FIVR), Ice Lake, subscriber only (general)

The magnets under the icy lake

Foundries IEDM 2020 Process Technologies Roadmaps Subscriber Only Content

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

May 21, 2021May 23, 2021 David Schor 3 nm, 4 nm, 4LPE, 4LPP, 5 nm, 5LPE, 5LPP, 7 nm, IEDM 2020, Samsung, Samsung Foundry, subscriber only (general)

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

Architectures Manycore Processors Subscriber Only Content

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI

May 16, 2021May 23, 2021 David Schor 7 nm, Esperanto, ET-Maxion, ET-Minion, ET-SoC-1, neural processors, RISC-V, subscriber only (general), TSMC

A look at Esperanto’s ET-SoC-1, the startup’s first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.