WikiChip Fuse
Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

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Nvidia Inference Research Chip Scales to Dozens of Chiplets

Nvidia recently presented a research chip comprising dozens of chiplets that enables them to scale from milliwatts to hundreds of watts in order to cater to different markets such as edge, mobile, automotive, and data center.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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A Look at NEC’s Latest Vector Processor, the SX-Aurora

A look at the NEC SX-Aurora, their latest vector processor – increasing compute while maintaining a high B/F through six HBM2 modules leveraging TSMC 2nd gen CoWoS technology. The SX-Aurora introduces a new form factor, system architecture, and execution model.

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Hot Chips 30: Intel Kaby Lake G

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

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ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.

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