WikiChip Fuse
TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

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CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

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OCP Makes a Push for an Open Chiplet Marketplace

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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A Look at NEC’s Latest Vector Processor, the SX-Aurora

A look at the NEC SX-Aurora, their latest vector processor – increasing compute while maintaining a high B/F through six HBM2 modules leveraging TSMC 2nd gen CoWoS technology. The SX-Aurora introduces a new form factor, system architecture, and execution model.

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