Skip to content
Sunday, February 5, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

Samsung

Foundries Roadmaps Subscriber Only Content 

Samsung Foundry On EUV, Pellicles, Capacity, and Yield

July 25, 2022July 25, 2022 David Schor 4 nm, 5 nm, Extreme Ultraviolet (EUV) Lithography, Samsung, Samsung Foundry, subscriber only (general)

Samsung Foundry talks about EUV, wafer capacity and mid-term plans,pPellicles, and advanced node yield.

Read more
Foundries Process Technologies Roadmaps 

Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

July 5, 2022July 5, 2022 David Schor 2 nm, 3 nm, 3GAAE, 3GAAP, 3GAE, 3GAP, 5LPE, GAAFET, nanosheet, Samsung, Samsung Foundry

Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements

Read more
Foundries IEDM 2021 Process Technologies Subscriber Only Content 

A Look At Samsung’s 4LPE Process

June 26, 2022June 26, 2022 David Schor 4 nm, 4LPE, 4LPP, FinFET, Samsung, Samsung Foundry, subscriber only (general)

A look at Samsung’s last leading-edge FinFET process node, 4nm 4LPE.

Read more
Foundries Process Technologies Subscriber Only Content 

Samsung 17nm follows Intel 16

May 22, 2022May 22, 2022 David Schor 14 nm, 14LPP, 17 nm, 17LPV, 28 nm, 28LPP, Intel, Intel Foundry Services (IFS), Samsung, Samsung Foundry, subscriber only (general)

Samsung follows Intel 16 with a low-cost high-performance, 17-nanometer, 17LPV node.

Read more
Architectures Neural Processors 

Samsung-Esperanto Concept AI-SSD Prototype

November 21, 2021November 21, 2021 David Schor AI-SSD, ASPLOS, ASPLOS 2021, Esperanto, Facebook, Samsung

Esperanto demonstrates a concept AI-SSD prototype in collaboration with Samsung aimed at accelerating data center workloads such as recommendation engines.

Read more
Circuit Design Foundries ISSCC 2021 Process Technologies Roadmaps Subscriber Only Content VLSI 2021 

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

July 8, 2021July 8, 2021 David Schor 3 nm, GAA, Samsung, Samsung Foundry, subscriber only (general)

Samsung tapes out 3nm GAA test vehicle as it inches towards mass production

Read more
Foundries IEDM 2020 Process Technologies Roadmaps Subscriber Only Content 

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

May 21, 2021June 24, 2021 David Schor 3 nm, 4 nm, 4LPE, 4LPP, 5 nm, 5LPE, 5LPP, 7 nm, IEDM 2020, Samsung, Samsung Foundry, subscriber only (general)

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

Read more
Foundries 

Q1 2021 Foundry Update: Spending Bonanza

May 18, 2021May 23, 2021 David Schor 10 nm, 3 nm, 5 nm, 7 nm, FinFET, GAA, Intel, Samsung, SMIC, TSMC

A look at the current state of leading-edge foundries for the first quarter of 2021.

Read more
Architectures Mobile Processors 

Samsung M5 Core Details Show Up

November 21, 2019May 25, 2021 David Schor 7 nm, 7LPP, ARM, ARMv8, ARMv8.2, Exynos, Samsung

Samsung details the high-level changes to the Exynos M5 core found in the Exynos 990.

Read more
ARM TechCon 2019 Process Technologies Roadmaps 

Samsung 5 nm and 4 nm Update

October 19, 2019May 25, 2021 David Schor 4LPE, 4nm, 5LPE, 5nm, Samsung

Update and analysis of Samsung’s upcoming 5-nanometer and 4-nanometer process technologies.

Read more
  • ← Previous

Top Six Articles

  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements
  • A Look At Intel 4 Process Technology
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • Intel Silently Launches Cannon Lake
  • A Look At AMD’s 3D-Stacked V-Cache

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

A Look At The Habana Inference And Training Neural Processors

A Look At The Habana Inference And Training Neural Processors

December 15, 2019May 25, 2021 David Schor
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

July 28, 2019May 25, 2021 David Schor
OCP Makes a Push for an Open Chiplet Marketplace

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020May 25, 2021 David Schor
IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor
TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

The NPU Inside Every Intel PC

The NPU Inside Every Intel PC

September 30, 2022September 30, 2022 David Schor
Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow

Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow

May 28, 2019May 25, 2021 David Schor
IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor
TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020May 25, 2021 David Schor
IBM Introduces Next-Gen Z  Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

September 14, 2019May 25, 2021 David Schor
Core i7-8700K overclockability silicon lottery stats

Core i7-8700K overclockability silicon lottery stats

November 12, 2017May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.