5 nm – WikiChip Fuse

Architectures Mobile Processors

Arm Unveils the Cortex-A78: When Less Is More

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A77, Cortex-A78

Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.

Architectures Mobile Processors

Arm Cortex-X1: The First From The Cortex-X Custom Program

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A78, Cortex-X, Cortex-X1

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new Cortex-X Custom Program.

Foundries Roadmaps

TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

May 14, 2020 David Schor 0 Comments 5 nm, TSMC

TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.

Foundries Process Technologies Roadmaps

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020 David Schor 6 Comments 3 nm, 5 nm, FinFET, N3, N5, N5P, N7, N7P, TSMC

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020 David Schor 4 Comments 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020 David Schor 0 Comments 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

Desktop Processors Mobile Processors Roadmaps Server Processors

Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

December 12, 2019 David Schor 0 Comments 16nm, 5 nm, China, DDR5, PCIe 4.0, x86, Zhaoxin

Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.