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TSMC Details 5 nm

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

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TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

7-nanometer contributes the lion’s share of wafer revenue to TSMC’s fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

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TSMC 5-Nanometer Update

An update on TSMC’s upcoming 5-nanometer process technology.

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TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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