Today TSMC announced it is extending its 5-nanometer node family with a new enhanced-performance N4P node.
TSMC ramped its 5-nanometer node (N5) early last year. The N5 node is said to deliver around 1.8x improvement in density along with 15% higher speed at iso-power or, alternatively, 30% lower power at the same speed. Since then TSMC also introduced an enhanced successor to N5 called N4. N4 is a derivative of N5 (which is TSMC includes it under the “5nm family”) very similar to the N6 node they introduced to enhance their N7 node. N4 is said to provide a small 6% die shrink through “standard cell innovation” and design rule changes that help realize better area efficiency. There are also some performance and power improvements through various BEOL enhancements. TSMC says that N4 will use EUV for more layers thereby reducing the number of steps and masks, thus offering a cost advantage.
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Today TSMC announced it is extending the 5-nanometer node family with one more node which is designed to offer easy migration from N5. The extended performance N4P node is a derivative of the N4 node which TSMC says will deliver 11% performance boost over the original N5 node or, alternatively, a 6% boost over N4. In terms of power efficiency, TSMC says the N4P node will offer a 22% improvement in power efficiency compared to N5.
In terms of transistor density, as with N4, N4P will also offer a 6% improvement in transistor density. In other words, both N4 and N4P should have similar transistor densities. TSMC also says that the N4P “lowers process complexity and improves wafer cycle time by reducing the number of masks.”
The N4 node is expected to enter risk production around this quarter. We expect the N4P node to follow with risk production early next year. TSMC expects the first products based on N4P technology to tape out by the second half of 2022.