Process Technologies

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

Interconnects Packaging Process Technologies May 17, 2020 3

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

Foundries Process Technologies Roadmaps April 17, 2020 3

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

TSMC Details 5 nm

Foundries IEDM 2019 ISSCC 2020 Process Technologies March 21, 2020 3

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

Interconnects Packaging Process Technologies March 3, 2020 0

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

TSMC Digs Trenches In Search Of Higher Performance

IEDM 2019 Interconnects Packaging Process Technologies December 14, 2019 0

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

UMC Rolls Out 22-Nanometer

Foundries Process Technologies December 13, 2019 0

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm and 28nm nodes.