Process Technologies

Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A

July 26, 2021July 26, 2021 David Schor Extreme Ultraviolet (EUV) Lithography, Intel, Intel 20A, Intel 3, Intel 4, Intel 7

Intel 2021 Process Technology Update: Intel 7, Intel 4, Intel 3, and Intel 20A

Foundries Process Technologies Roadmaps

Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp

July 26, 2021July 26, 2021 David Schor 20 Å, GAA, Intel, Intel 20A, PowerVia, RibbonFET

Intel announces Intel 20Å Node which will feature RibbonFET devices, PowerVia, and is set to ramp 2024.

Circuit Design Foundries ISSCC 2021 Process Technologies Roadmaps Subscriber Only Content VLSI 2021

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

July 8, 2021July 8, 2021 David Schor 3 nm, GAA, Samsung, Samsung Foundry, subscriber only (general)

Samsung tapes out 3nm GAA test vehicle as it inches towards mass production

Foundries Process Technologies Roadmaps Subscriber Only Content

TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

July 6, 2021July 6, 2021 David Schor 5 nm, 7 nm, HPC, N5A, N5HPC, N6RF, N7HPC, subscriber only (general)

A TSMC 2021 foundry update: automotive, networking, and HPC roadmap.

Foundries Process Technologies Roadmaps Subscriber Only Content

TSMC 2021 Foundry Update: Foundry Roadmap

July 6, 2021July 6, 2021 David Schor 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N2 2 nm, N3, N4, N5, N6, N7, subscriber only (general), TSMC

TSMC 2021 foundry update

Foundries IEDM 2020 Process Technologies Subscriber Only Content

Intel Talks 10nm DTCO, EUV Benefits

June 22, 2021June 22, 2021 David Schor 10 nm, 5 nm, 7 nm, EUV, IEDM, IEDM 2020, Intel, subscriber only (general)

Intel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.

Foundries IEDM 2020 Process Technologies Roadmaps Subscriber Only Content

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

May 21, 2021June 24, 2021 David Schor 3 nm, 4 nm, 4LPE, 4LPP, 5 nm, 5LPE, 5LPP, 7 nm, IEDM 2020, Samsung, Samsung Foundry, subscriber only (general)

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

Interconnects Packaging Process Technologies

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020May 23, 2021 David Schor 2.5D packaging, 3D packaging, Co-EMIB, EMIB, Foveros, Intel

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Foundries Process Technologies Roadmaps

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020May 25, 2021 David Schor 3 nm, 5 nm, FinFET, N3, N5, N5P, N7, N7P, TSMC

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020May 25, 2021 David Schor 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

← Previous