Process Technologies

Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem

David SchorARM TechCon 2018, Foundries, Packaging, Process TechnologiesOctober 28, 2018 Tagged 2.5D packaging, 3D packaging, 3GAAE, 3GAAP, 3GAE, 3nm, 4LPE, 4LPP, 5LPE, 5nm, 7LPP, 7nm, EUV, Packaging, Samsung

Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.

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Nantero’s NRAM, A Universal Memory Candidate?

David SchorHot Chips 30, Interconnects, Process TechnologiesSeptember 22, 2018 Tagged 28nm, carbon nanotube, carbon nanotubes, CNTs, Nantero, non-volatile memory, NRAM, process technology, storage-class memory

Presented at Hot Chips 30, a look at Nantero’s NRAM, a high-performance carbon nanotube-based memory billed as a DRAM successor.

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VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

David SchorProcess Technologies, VLSI 2018August 4, 2018 Tagged 7LPP, 7nm, EUV, process technology, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 2nd generation 7nm process that was recently disclosed at the 38th Symposium on VLSI Technology.

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VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

David SchorFoundries, Process Technologies, VLSI 2018July 22, 2018 Tagged 12LP, 12nm, 14LPP, 14nm, FinFET, GlobalFoundries, process technology

A look at GlobalFoundries 12nm Leading Performance technology, 12LP, an enhanced 14nm process. The process was recently presented at the 2018 Symposia on VLSI Technology and Circuits.

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VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

David SchorProcess Technologies, VLSI 2018July 1, 2018 Tagged 10LPE, 10LPP, 10nm, 8LPP, 8nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

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VLSI 2018: Samsung’s 11nm nodelet, 11LPP

David SchorProcess Technologies, VLSI 2018June 30, 2018 Tagged 10nm, 11LPP, 11nm, 14nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 11nm 11LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium

David SchorCircuit Design, Process TechnologiesJune 15, 2018 Tagged 10nm, cobalt, Intel, Intel Custom Foundry, metallization stack, ruthenium, TechInsights

WikiChip takes another look at Intel’s 10-nanometer standard cell design and discusses TechInsights findings of the first 10nm-based chip, the i3-8121U.

GlobalFoundries 14HP process, a marriage of two technologies

David SchorProcess TechnologiesMarch 2, 2018 Tagged 14HP, 14nm, FinFET, GlobalFoundries, IBM, process technology, silicon on insulator, SOI

As IBM starts shipping their latest server microprocessors we take a look at the process technology that’s enabling those capabilities. Though largely thought to be the same as the original process IBM detailed back in 2014, following their fab selloff the process has undergone some unique changes making it a distinctly GlobalFoundries process now.

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IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

David SchorIEDM 2017, ISSCC 2018, Process TechnologiesFebruary 17, 2018 Tagged 10nm, FinFET, IEDM, IEDM 2017, Intel, ISSCC, ISSCC 2018, process technology

At IEDM 2017 and ISSCC 2018 Intel detailed their upcoming 10nm node, an aggressively scaled 7nm-class process technology that features new scaling accelerators as well as cobalt interconnect for the first time in high-volume manufacturing.

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IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

David SchorIEDM 2017, Process TechnologiesDecember 21, 2017 Tagged 7LP, 7nm, AMD, EUV, FinFET, GlobalFoundries, IBM, IEDM, IEDM 2017, process technology, SADP, SAQP

At the 2017 IEDM GlobalFoundries detailed their 7nm Leading Performance (7LP) process, an aggressively scaled version of their 14nm process optimized for next-generation mobile, SoC, and high-performance applications.

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