Process Technologies

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

David SchorArchitectures, Interconnects, Packaging, Process TechnologiesSeptember 21, 2019 Tagged 12LP, 12nm, 3D packaging, ARM, design-for-test, GlobalFoundries, hybrid bonding

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

David SchorPackaging, Process Technologies, SEMICON West 2019, VLSI 2019July 28, 2019 Tagged 3D packaging, 3nm, 5nm, 6nm, 7nm, CoWoS, InFO, InFO_AiP, InFO_MS, InFO_oS, N5, N5P, N6, N7, N7P, SemiConWest, SoIC, VLSI 2019, VLSI Symposium

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

David SchorProcess Technologies, VLSI 2019June 16, 2019 Tagged 7HPC, 7nm, FinFET, SDM845, SDM855, Snapdragon 800, Snapdragon 855, TSMC, VLSI 2019, VLSI Symposium

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

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Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

David SchorFoundries, Interconnects, Packaging, Process TechnologiesMay 11, 2019 Tagged 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Samsung Ramps 7nm, Preps 5nm, And Adds 6nm

David SchorProcess TechnologiesApril 16, 2019 Tagged 5 nm, 6 nm, EUV

Samsung is announcing the completion of their 5-nanometer process design and the ramping of their 7 nm process.

TSMC Announces 6-Nanometer Process

David SchorProcess TechnologiesApril 16, 2019 Tagged 6 nm, EUV, TSMC

TSMC announces the 6-nanometer process, an enhanced 7 nm EUV node.

TSMC Starts 5-Nanometer Risk Production

David SchorProcess TechnologiesApril 6, 2019 Tagged 5 nm, 7 nm, FinFET, risk production, TSMC

TSMC 5-nanometer node has entered risk production with PDKs available for production design. Here’s is our initial density estimates.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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IBM Chooses Samsung 7nm EUV for Next-Gen POWER and Z Microprocessors

David SchorFoundries, Process Technologies, Roadmaps, Server ProcessorsDecember 20, 2018 Tagged 7LPP, 7nm, Common Platform Alliance, EUV, IBM, POWER, POWER10, Samsung, Z

IBM partners up with Samsung 7nm EUV process for their next-generation of POWER and Z microprocessors.