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TSMC Details 5 nm

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

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TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

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TSMC Digs Trenches In Search Of Higher Performance

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

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UMC Rolls Out 22-Nanometer

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm and 28nm nodes.

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Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

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TSMC 5-Nanometer Update

An update on TSMC’s upcoming 5-nanometer process technology.

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Samsung 5 nm and 4 nm Update

Update and analysis of Samsung’s upcoming 5-nanometer and 4-nanometer process technologies.

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Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET

Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.

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TSMC N7+ EUV Process Starts Shipping

TSMC announces its N7+ process which entered HVM earlier this year is now shipping products to market.

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GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

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