neural processors

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

Architectures Neural Processors February 10, 2020 0

Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an ultra-low-power dedicated NPU for embedded applications.

Arm Ethos is for Ubiquitous AI At the Edge

Architectures Linley Processor Conference Neural Processors February 6, 2020 0

Arm’s Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.

Intel Axes Nervana Just Two Months After Launch

Architectures Neural Processors Roadmaps February 3, 2020 4

Intel axes Nervana in favor of Habana.

Centaur New x86 Server Processor Packs an AI Punch

Architectures Neural Processors Server Processors January 24, 2020 3

A look at Centaur’s new server-class x86 SoC with an integrated neural processor.

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

Architectures Circuit Design Manycore Processors Network-on-Chip Neural Processors VLSI 2019 January 12, 2020 0

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

A Look At The Habana Inference And Training Neural Processors

Architectures Hot Chips 31 Neural Processors December 15, 2019 3

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Architectures Embedded Processors Neural Processors Server Processors December 9, 2019 3

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

Intel Starts Shipping Initial Nervana NNP Lineup

Neural Processors Supercomputing 19 December 6, 2019 1

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

Architectures Neural Processors Supercomputers Supercomputing 19 November 24, 2019 0

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

Architectures Hot Chips 31 Interconnects Neural Processors Packaging November 16, 2019 0

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.