neural processors – WikiChip Fuse

Architectures Neural Processors

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

February 10, 2020 David Schor 0 Comments ARM, Arm Ethos, Cortex, Cortex-M55, inference, neural processors

Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an ultra-low-power dedicated NPU for embedded applications.

Architectures Linley Processor Conference Neural Processors

Arm Ethos is for Ubiquitous AI At the Edge

February 6, 2020 David Schor 0 Comments AI, ARM, Arm Ethos, Arm ML Processor (MLP), inference, neural processors

Arm’s Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.

Architectures Neural Processors Roadmaps

Intel Axes Nervana Just Two Months After Launch

February 3, 2020 David Schor 4 Comments 16nm, AI, Habana Labs, Intel, Nervana, neural processors, NNP, NNP-I, NNP-T

Intel axes Nervana in favor of Habana.

Architectures Neural Processors Server Processors

Centaur New x86 Server Processor Packs an AI Punch

January 24, 2020 David Schor 3 Comments 16nm, AI, AVX-512, Centaur Technology, CHA, inference, neural processors, x86

A look at Centaur’s new server-class x86 SoC with an integrated neural processor.

Architectures Circuit Design Manycore Processors Network-on-Chip Neural Processors VLSI 2019

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

January 12, 2020 David Schor 0 Comments 16nm, AI, Celerity, DARPA, DARPA CRAFT, inference, Network-on-Chip (NoC), neural processors, PLL, RISC-V, VLSI, VLSI 2019

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

Architectures Hot Chips 31 Neural Processors

A Look At The Habana Inference And Training Neural Processors

December 15, 2019 David Schor 3 Comments 16nm, AI, Gaudi, Goya, Habana Labs, Hot Chips, Hot Chips 31, inference, neural processors, OCP Accelerator Module (OAM), training

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

Architectures Embedded Processors Neural Processors Server Processors

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

December 9, 2019 David Schor 3 Comments 16nm, AVX-512, Centaur Technology, CHA, inference, neural processors, VIA Technologies, x86

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

Neural Processors Supercomputing 19

Intel Starts Shipping Initial Nervana NNP Lineup

December 6, 2019 David Schor 1 Comment AI, inference, Intel, neural processors, NNP, NNP-T, NPP-L, OCP Accelerator Module (OAM), Spring Crest, Spring Hill, Supermicro, training

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

Architectures Neural Processors Supercomputers Supercomputing 19

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

November 24, 2019 David Schor 0 Comments 12 nm, AI, GRAPE, multi-chip package, neural processors, Preferred Networks, Supercomputers, training

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).

Architectures Hot Chips 31 Interconnects Neural Processors Packaging

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

November 16, 2019 David Schor 0 Comments 16nm, AI, Cerebras, Hot Chips, Hot Chips 31, neural processors, training, Wafer-Scale Engine (WSE)

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

← Previous