David Schor

Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

April 27, 2021April 27, 2021 David Schor 0 Comments ARM, ARMv9, bfloat16, Neoverse N, Neoverse V, Perseus, Scalable Vector Extension (SVE), Scalable Vector Extension 2 (SVE2), Zeus

Arm launches its next-generation server CPUs – Neoverse N2 and Neoverse V1 (formerly Perseus and Zeus). Targeting high-performance servers and the HPC market, the new cores bring 1.4-1.5x higher IPC , SVE support, BFloat16, and the ARMv9 architecture.

Architectures Server Processors

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021April 6, 2021 David Schor 1 Comment 10nm, AVX-512, Ice Lake, Intel, Sunny Cove, x86, Xeon Gold, Xeon Platinum, Xeon Scalable, Xeon Silver

Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

Roadmaps

Arm Highlights Near-Term Roadmap

April 4, 2021April 5, 2021 David Schor 0 Comments ARM, ARMv9, Makalu, Matterhorn, Neoverse N, Neoverse V

Along with the launch of ARMv9, Arm highlighted its near-term roadmap promising strong generational performance improvements.

Architectures Roadmaps

Arm Launches ARMv9

March 30, 2021March 30, 2021 David Schor 4 Comments ARM, ARMv8, ARMv9, Confidential Compute Architecture (CCA), Scalable Vector Extension (SVE), Scalable Vector Extension 2 (SVE2)

Ten years after launching ARMv8, Arm is launching the ARMv9 architecture for the next decade of compute.

Roadmaps Server Processors

Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

September 22, 2020September 30, 2020 David Schor 3 Comments ARM, bfloat16, neoverse, Neoverse N, Neoverse V, Perseus, Poseidon, Scalable Vector Extension (SVE), Zeus

Arm updates its Neoverse roadmap with the Neoverse N2 and V1, introducing SVE support for the first time as well as bfloat16 operations. Like the Cortex-X series, the Neoverse V-series will ease its power and area constraints in favor of higher performance.

Architectures

The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

June 29, 2020September 19, 2020 David Schor 10 Comments Advanced Matrix Extension (AMX), AI, Intel, matrices, Sapphire Rapids, x86

Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.

Architectures Embedded Processors

Arm’s New Cortex-M55 Breathes Helium

June 20, 2020 David Schor 0 Comments AI, ARM, ARMv8, Cortex, Cortex-M, Cortex-M55, Helium, M-Profile Vector Extension (MVE)

A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.

Mobile Processors

Intel Launches Lakefield: An Experiment With Multiple New Technologies

June 15, 2020 David Schor 3 Comments 10 nm, 22 nm, 22FFL, 3D packaging, Core i3, Core i5, Foveros, Intel, Lakefield, Sunny Cove, Tremont

Intel launches Lakefield, a 3D SoC with a new form factor for ultra-mobile devices. This microprocessor allows the chip giant to dabble with a number of new complementary technologies that could potentially find broader uses in the future.