WikiChip Fuse
Ayar Labs Realizes Co-Packaged Silicon Photonics

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

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TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

7-nanometer contributes the lion’s share of wafer revenue to TSMC’s fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

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A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

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AMD Launches New Entry-Level Mobile ‘Dali’ Processors

AMD launches new value and entry-level mobile processors, codenamed Dali.

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OCP Bunch of Wires: A New Open Chiplets Interface For Organic Substrates

A look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.

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OCP Makes a Push for an Open Chiplet Marketplace

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

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Chuck Peddle: Personal Computer Pioneer, Dies At 82

Personal computer pioneer, Chuck Peddle, dies at 82.

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A Look At The Habana Inference And Training Neural Processors

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

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TSMC Digs Trenches In Search Of Higher Performance

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

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UMC Rolls Out 22-Nanometer

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm and 28nm nodes.

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