David Schor

AMD Announces Threadripper 2, Chiplets Aid Core Scaling

David SchorDesktop ProcessorsAugust 7, 2018 Tagged 12LP, 12nm, AMD, HEDT, Ryzen, Threadripper, Threadripper 2, x86, Zen+

AMD announces their second-generation Threadripper processors with up to 32 cores based on their 12nm Zen+ microarchitecture.

VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

David SchorProcess Technologies, VLSI 2018August 4, 2018 Tagged 7LPP, 7nm, EUV, process technology, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 2nd generation 7nm process that was recently disclosed at the 38th Symposium on VLSI Technology.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

David SchorInterconnectsJuly 24, 2018 Tagged Advanced Interface Bus, AIB, DARPA, EMIB, Intel, interconnects, Packaging

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

David SchorFoundries, Process Technologies, VLSI 2018July 22, 2018 Tagged 12LP, 12nm, 14LPP, 14nm, FinFET, GlobalFoundries, process technology

A look at GlobalFoundries 12nm Leading Performance technology, 12LP, an enhanced 14nm process. The process was recently presented at the 2018 Symposia on VLSI Technology and Circuits.

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