WikiChip Fuse
UMC Rolls Out 22-Nanometer

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path from existing 40nm and 28nm nodes.

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Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.

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Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

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Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

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Intel Starts Shipping Initial Nervana NNP Lineup

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

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NEC Refreshes SX-Aurora Vector Engine, Outlines Roadmap

NEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.

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Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).

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Samsung M5 Core Details Show Up

Samsung details the high-level changes to the Exynos M5 core found in the Exynos 990.

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SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

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A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

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