David Schor

Desktop Processors Mobile Processors

Intel Launches 10th Gen Comet Lake vPro Processors

May 13, 2020 David Schor 0 Comments Comet Lake, Core i5, Core i7, Core i9, Intel, vPro

Intel launches its 10th-generation Comet Lake-based vPro processors.

Desktop Processors Mobile Processors

Intel Launches Entry-Level Comet Lake Xeon Ws

May 13, 2020 David Schor 0 Comments 14 nm, Comet Lake, Intel, Xeon W

Intel launches a new series of Xeon W processors for entry-level workstations based on Comet Lake.

Mobile Processors

AMD Launches Ryzen Pro 4000 Series

May 7, 2020 David Schor 0 Comments 7 nm, AMD, Ryzen, Ryzen Pro, Zen 2

AMD launches its Zen 2-based Ryzen Pro 4000 series for enterprise customers.

Desktop Processors

Intel Launches 10th Gen Comet Lake Desktop Processors

April 30, 2020 David Schor 14 nm, Comet Lake, Core i3, Core i5, Core i7, Core i9, Intel

Intel launches 10th Generation Core desktop processors, formerly codename Comet Lake. The new lineup brings 22 new chips with up to 10 cores and 20 threads with turbo frequencies of up to 5.3 GHz.

Foundries Process Technologies Roadmaps

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020 David Schor 4 Comments 3 nm, 5 nm, FinFET, N3, N5, N5P, N7, N7P, TSMC

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

Interconnects Packaging Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020 David Schor 0 Comments co-packaged optics (CPO), co-packaging, Ranovus, Ranovus Odin, silicon photonics

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

Architectures Hot Chips 31 IEDM 2019 ISSCC 2020

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020 David Schor 1 Comment 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020 David Schor 4 Comments 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

Architectures Circuit Design ISSCC 2020

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020 David Schor 5 Comments 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020 David Schor 0 Comments 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.