David Schor

Intel Talks 10nm DTCO, EUV Benefits

June 22, 2021June 22, 2021 David Schor 10 nm, 5 nm, 7 nm, EUV, IEDM, IEDM 2020, Intel, subscriber only (general)

Intel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.

Architectures FPGAs Subscriber Only Content

Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

June 13, 2021June 13, 2021 David Schor 16 nm, Diamond Mesa, eASIC Nextreme, Intel, Intel eASIC, Structured ASIC, subscriber only (general)

With Intel’s acquisition of eASIC in 2018, the company’s latest product – codenamed Diamond Mesa – attempts to bridge the gap between full ASIC and FPGAs.

IEDM 2020 Interconnects Packaging Subscriber Only Content

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.