Intel

Ayar Labs Realizes Co-Packaged Silicon Photonics

Architectures Circuit Design Hot Chips 31 Interconnects Packaging January 19, 2020 0

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

IEDM 2019 Process Technologies Roadmaps December 10, 2019 1

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

Intel Starts Shipping Initial Nervana NNP Lineup

Neural Processors Supercomputing 19 December 6, 2019 0

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 November 17, 2019 1

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

Intel Announces Keem Bay: 3rd Generation Movidius VPU

Neural Processors November 12, 2019 0

Intel announces Keem Bay, its 3rd-generation Movidius VPU edge inference processor.

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

Architectures Hot Chips 31 Linley Processor Conference Neural Processors November 10, 2019 1

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

FPGAs Packaging November 7, 2019 0

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.