WikiChip Fuse
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

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Intel Starts Shipping Initial Nervana NNP Lineup

Intel starts shipping its initial Nervana NNP lineup for both inference and training acceleration with four initial models in three different form factors.

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SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

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Intel Announces Keem Bay: 3rd Generation Movidius VPU

Intel announces Keem Bay, its 3rd-generation Movidius VPU edge inference processor.

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A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

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Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

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Intel Core i9-9900KS Special Edition Full Specs and Availability Announced

Intel announces the full specification, pricing, and availability of the Core i9-9900KS Special Edition.

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Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.

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Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET

Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.

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Intel Launches Mainstream Cascade Lake Xeon W Workstation Processors

Intel launches mainstream W-2200 series Xeon W workstation microprocessors based on the Cascade Lake microarchitecture.

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