A Look At AMD’s 3D-Stacked V-Cache
[Subscription] A technical look at AMD’s 3D-Stacked V-Cache
Read more[Subscription] A technical look at AMD’s 3D-Stacked V-Cache
Read moreSiFive announces new high-performance RISC-V cores, bifurcating the Performance family into performance and efficiency cores.
Read moreAlibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip
Read moreIntel unveiled Sapphire Rapids, its next-generation server CPUs
Read moreIntel details Golden Cove, the company’s next-generation big core for client and server SoCs
Read moreThe IEEE Symposium on High-Performance Chips Program Committee announced the program for the 2021 Hot Chips 33 conference.
Read moreArm launches its next-generation server CPUs – Neoverse N2 and Neoverse V1 (formerly Perseus and Zeus). Targeting high-performance servers and the HPC market, the new cores bring 1.4-1.5x higher IPC , SVE support, BFloat16, and the ARMv9 architecture.
Read moreIntel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.
Read moreArm updates its Neoverse roadmap with the Neoverse N2 and V1, introducing SVE support for the first time as well as bfloat16 operations. Like the Cortex-X series, the Neoverse V-series will ease its power and area constraints in favor of higher performance.
Read moreIBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including 4-bit integers, and new instruction prefixes. IBM plans on presenting POWER10 at Hot Chips 32.
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