Server Processors

A Look At AMD’s 3D-Stacked V-Cache

December 27, 2022December 27, 2022 David Schor 3D V-Cache, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, subscriber only (general), System on Integrated Chips (SoIC)

[Subscription] A technical look at AMD’s 3D-Stacked V-Cache

Embedded Processors Mobile Processors Roadmaps Server Processors

SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

November 1, 2022November 2, 2022 David Schor P470, P670, RISC-V, SiFive

SiFive announces new high-performance RISC-V cores, bifurcating the Performance family into performance and efficiency cores.

Architectures Server Processors

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor 5 nm, Alibaba, Apsara Conference 2021, ARM, ARMv9, Panjiu, RISC-V, T-Head, TSMC, Xuantie, Yitian 710

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

Architectures Server Processors

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor Advanced Matrix Extension (AMX), AVX-512, Golden Cove, Intel, Intel 7, Sapphire Rapids, x86

Intel unveiled Sapphire Rapids, its next-generation server CPUs

Architectures Desktop Processors Mobile Processors Server Processors

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor Alder Lake, Golden Cove, Intel, Intel 7, Sapphire Rapids, x86

Intel details Golden Cove, the company’s next-generation big core for client and server SoCs

Architectures Graphics Processors Hot Chips 33 Mobile Processors Neural Processors Server Processors Vector Processors

Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

May 13, 2021May 23, 2021 David Schor AMD, ARM, Cerebras, Esperanto, Hot Chips, Hot Chips 33, Intel, Nvidia

The IEEE Symposium on High-Performance Chips Program Committee announced the program for the 2021 Hot Chips 33 conference.

Architectures Server Processors

Arm Launches New Neoverse N2 and V1 Server CPUs: 1.4x-1.5x IPC, SVE, and ARMv9

April 27, 2021May 23, 2021 David Schor ARM, ARMv9, bfloat16, Neoverse N, Neoverse V, Perseus, Scalable Vector Extension (SVE), Scalable Vector Extension 2 (SVE2), Zeus

Arm launches its next-generation server CPUs – Neoverse N2 and Neoverse V1 (formerly Perseus and Zeus). Targeting high-performance servers and the HPC market, the new cores bring 1.4-1.5x higher IPC , SVE support, BFloat16, and the ARMv9 architecture.

Architectures Server Processors

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor 10nm, AVX-512, Ice Lake, Intel, Sunny Cove, x86, Xeon Gold, Xeon Platinum, Xeon Scalable, Xeon Silver

Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

Roadmaps Server Processors

Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

September 22, 2020May 23, 2021 David Schor ARM, bfloat16, neoverse, Neoverse N, Neoverse V, Perseus, Poseidon, Scalable Vector Extension (SVE), Zeus

Arm updates its Neoverse roadmap with the Neoverse N2 and V1, introducing SVE support for the first time as well as bfloat16 operations. Like the Cortex-X series, the Neoverse V-series will ease its power and area constraints in favor of higher performance.

Hot Chips 32 Server Processors

IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

May 23, 2020May 23, 2021 David Schor bfloat16, Hot Chips, Hot Chips 32, IBM, OpenPOWER, POWER, Power ISA, POWER10

IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including 4-bit integers, and new instruction prefixes. IBM plans on presenting POWER10 at Hot Chips 32.

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