Circuit Design

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

Architectures Circuit Design ISSCC 2020 March 8, 2020 5

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors March 1, 2020 0

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Radeon RX 5700: Navi and the RDNA Architecture

Architectures Circuit Design Graphics Processors ISSCC 2020 February 23, 2020 1

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Ayar Labs Realizes Co-Packaged Silicon Photonics

Architectures Circuit Design Hot Chips 31 Interconnects Packaging January 19, 2020 0

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

Architectures Circuit Design Manycore Processors Network-on-Chip Neural Processors VLSI 2019 January 12, 2020 0

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

Architectures Circuit Design ERI Summit 2019 FPGAs July 20, 2019 0

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

Circuit Design Floorplanning IEDM 2018 Process Technologies January 6, 2019 3

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

Hot Chips 30: Intel Kaby Lake G

Circuit Design Hot Chips 30 Packaging September 9, 2018 0

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

Hot Chips 30: AMD Raven Ridge

Architectures Circuit Design Hot Chips 30 August 26, 2018 0

Overview of AMD Raven Ridge APUs that were recently detailed at Hot Chips 30.

A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium

Circuit Design Process Technologies June 15, 2018 5

WikiChip takes another look at Intel’s 10-nanometer standard cell design and discusses TechInsights findings of the first 10nm-based chip, the i3-8121U.