Circuit Design

Hot Chips 30: Intel Kaby Lake G

David SchorCircuit Design, Hot Chips 30, PackagingSeptember 9, 2018 Tagged 14nm, 2.5D packaging, 3D packaging, AMD, CPU, EMIB, GPU, Intel, Kaby Lake, Kaby Lake G, multi-chip package, Radeon Vega, x86

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

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Hot Chips 30: AMD Raven Ridge

David SchorArchitectures, Circuit Design, Hot Chips 30August 26, 2018 Tagged 14LPP, 14nm, AMD, AMD's infinity fabric, APU, Hot Chips, Hot Chips 30, Radeon Vega, Raven Ridge, Vega, x86, Zen

Overview of AMD Raven Ridge APUs that were recently detailed at Hot Chips 30.

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A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium

David SchorCircuit Design, Process TechnologiesJune 15, 2018 Tagged 10nm, cobalt, Intel, Intel Custom Foundry, metallization stack, ruthenium, TechInsights

WikiChip takes another look at Intel’s 10-nanometer standard cell design and discusses TechInsights findings of the first 10nm-based chip, the i3-8121U.

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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A look at Nvidia’s NVLink interconnect and the NVSwitch

David SchorArchitectures, Circuit Design, Conferences, Floorplanning, Graphics ProcessorsMay 6, 2018 Tagged 12FFN, 12nm, AI, DGX-1, DGX-2, GPU, Interconnect, Nvidia, NVLink, NVSwitch, Pascal, Volta

A look at Nvidia’s NVLink interconnect and the 2-billion transistor NVSwitch that is powering Nvidia’s latest DGX-2 deep learning machine.

QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

David SchorArchitectures, Circuit Design, ISSCC 2018, Neural ProcessorsApril 25, 2018 Tagged 3D packaging, 40 nm, 40LP, AI, die stacking, Hokkaido University, ISSCC, ISSCC 2018, Keio University, process technology, TCI, ThruChip Interface, TSMC, TSV

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

AMD’s Zen CPU Complex, Cache, and SMU

David SchorArchitectures, Circuit Design, ISSCC 2018April 18, 2018 Tagged 14LPP, 14nm, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

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ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 24, 2018 Tagged 14nm, 2D packaging, AMD, AMD's infinity fabric, EPYC, multi-chip package, Ryzen, x86, Zen

A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.

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ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor

David SchorArchitectures, Circuit Design, Embedded Processors, ISSCC 2018March 17, 2018 Tagged 65nm, crypto engine, DTLS, edge computing, IoT, ISSCC, ISSCC 2018, MIT, RISC-V

In recent years, IoT devices have been plagued with security issues. Memory and energy constraints of those low-power devices mean there is very little headroom for complex security implementations. At ISSCC 2018, a team of MIT researchers has attempted to address this problem with their low-power fully in-hardware crypto engine IoT RISC-V processor.

ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 9, 2018 Tagged 14nm, floorplan, Intel, ISSCC, ISSCC 2018, Skylake, Skylake-SP, x86, Xeon Scalable

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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