Circuit Design

A Look At AMD’s 3D-Stacked V-Cache

December 27, 2022December 27, 2022 David Schor 3D V-Cache, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, subscriber only (general), System on Integrated Chips (SoIC)

[Subscription] A technical look at AMD’s 3D-Stacked V-Cache

Circuit Design Foundries ISSCC 2021 Process Technologies Roadmaps Subscriber Only Content VLSI 2021

Samsung 3nm GAA Inches Towards Productization With SRAM, SoC Test Vehicles

July 8, 2021July 8, 2021 David Schor 3 nm, GAA, Samsung, Samsung Foundry, subscriber only (general)

Samsung tapes out 3nm GAA test vehicle as it inches towards mass production

Architectures Circuit Design ISSCC 2020

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020May 25, 2021 David Schor 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020May 25, 2021 David Schor 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Architectures Circuit Design Graphics Processors ISSCC 2020

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020May 25, 2021 David Schor 7 nm, AMD, ISSCC, ISSCC 2020, N7P, Navi, Radeon, Radeon RX 5700

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Architectures Circuit Design Hot Chips 31 Interconnects Packaging

Ayar Labs Realizes Co-Packaged Silicon Photonics

January 19, 2020May 25, 2021 David Schor 45 nm, 45RFSOI, Ayar Labs, chiplet, GlobalFoundries, GlobalFoundries Technology Conference (GTC), Hot Chips, Hot Chips 31, Intel, multi-chip package, Photonics, silicon photonics, Stratix 10, TeraPHY

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

Architectures Circuit Design Manycore Processors Network-on-Chip Neural Processors VLSI 2019

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

January 12, 2020May 25, 2021 David Schor 16nm, AI, Celerity, DARPA, DARPA CRAFT, inference, Network-on-Chip (NoC), neural processors, PLL, RISC-V, VLSI, VLSI 2019

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

Architectures Circuit Design ERI Summit 2019 FPGAs

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

July 20, 2019May 25, 2021 David Schor 45 nm, 45RFSOI, Advanced Interface Bus (AIB), Ayar Labs, chiplet, DARPA, EMIB, ERI Summit, ERI Summit 2019, FPGA, GlobalFoundries, Photonics, RISC-V, Stratix 10

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

Circuit Design Floorplanning IEDM 2018 Process Technologies

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.