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Tuesday, January 19, 2021
Latest:
  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
  • Arm’s New Cortex-M55 Breathes Helium
  • Intel Launches Lakefield: An Experiment With Multiple New Technologies
  • Arm Unveils the Cortex-A78: When Less Is More
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Radeon

Architectures Circuit Design Graphics Processors ISSCC 2020 

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020 David Schor 1 Comment 7 nm, AMD, ISSCC, ISSCC 2020, N7P, Navi, Radeon, Radeon RX 5700

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Read more
CES 2018 Processors 

AMD Tech Day: the momentum continues with new products, new prices, and 12nm and 7nm announcements

January 8, 2018 David Schor 0 Comments 12nm, 7nm, AM4, AMD, GlobalFoundries, Navi, Radeon, Radeon Vega, Ryzen, Ryzen Mobile, Ryzen Pro, Vega, x86, Zen, Zen 2, Zen 3

As they continue on building momentum, AMD held an impressive Tech Day at CES 2018 unveiling a series of products and detailing their aggressive roadmap going forward.

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CES 2018 Mobile Processors 

Intel launches 8th Gen Core with Radeon RX Vega Graphics

January 7, 2018 David Schor 0 Comments 14 nm, AMD, EMIB, GPU, HBM, Intel, Kaby Lake, Radeon, x86

At CES 2018 Intel announced the first series of the much anticipated Core i5 and i7 chips with Radeon graphics. Those parts incorporate a Kaby Lake microprocessor, a Vega M GPU, and 4 GiB of HBM2 cache.

Read more

Top Six Articles

  • TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
  • IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects
  • TSMC Details 5 nm
  • ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging
  • TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter
  • VLSI 2018: Samsung’s 2nd Gen 7nm, EUV Goes HVM

Recent

  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
  • Arm’s New Cortex-M55 Breathes Helium

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
  • Intel Launches Lakefield: An Experiment With Multiple New Technologies

    Intel Launches Lakefield: An Experiment With Multiple New Technologies

    June 15, 2020 David Schor 3
  • Arm Unveils the Cortex-A78: When Less Is More

    Arm Unveils the Cortex-A78: When Less Is More

    May 26, 2020 David Schor 0
  • Arm Cortex-X1: The First From The Cortex-X Custom Program

    Arm Cortex-X1: The First From The Cortex-X Custom Program

    May 26, 2020 David Schor 0
  • Comment
  • Recent
  • Steffen Eilers says:

    Yes....

  • Steffen says:

    Really exited for the time when ARM tries to serio...

  • Piotr says:

    Depends on what you're comparing. N6 manufacturing...

  • espinozahg says:

    Hey, everybody talks about GPU FLOPS but nobody ab...

  • Filipe says:

    O bom é q a arm tá longe de alcançar esse pata...

  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
    Arm’s New Cortex-M55 Breathes Helium

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
    Intel Launches Lakefield: An Experiment With Multiple New Technologies

    Intel Launches Lakefield: An Experiment With Multiple New Technologies

    June 15, 2020 David Schor 3
    Arm Unveils the Cortex-A78: When Less Is More

    Arm Unveils the Cortex-A78: When Less Is More

    May 26, 2020 David Schor 0

    Random Picks

    ASML Q4: NXE:3400C Machines Ramp; Strong Growth Due to EUV in 2020

    ASML Q4: NXE:3400C Machines Ramp; Strong Growth Due to EUV in 2020

    January 22, 2020 David Schor 0
    Intel Starts Shipping Initial Nervana NNP Lineup

    Intel Starts Shipping Initial Nervana NNP Lineup

    December 6, 2019 David Schor 1
    IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

    IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

    May 23, 2020 David Schor 0
    VLSI 2018: Next Week’s Samsung and GlobalFoundries Papers

    VLSI 2018: Next Week’s Samsung and GlobalFoundries Papers

    June 17, 2018 David Schor 0
    TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

    TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

    March 3, 2020 David Schor 0

    Random Tags

    2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 12nm 14 nm 16nm AI AMD ARM ARMv8 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET Foveros FPGA GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen Zen 2

    x86 WorldView All

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
    Architectures 

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10

    Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.

    Centaur New x86 Server Processor Packs an AI Punch
    Architectures Neural Processors Server Processors 

    Centaur New x86 Server Processor Packs an AI Punch

    January 24, 2020 David Schor 3
    Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs
    Desktop Processors Mobile Processors Roadmaps Server Processors 

    Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

    December 12, 2019 David Schor 0
    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512
    Architectures Embedded Processors Neural Processors Server Processors 

    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

    December 9, 2019 David Schor 3
    SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
    Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 

    SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

    November 17, 2019 David Schor 1
    AMD Announces 3rd Gen Ryzen Threadripper
    Desktop Processors Server Processors 

    AMD Announces 3rd Gen Ryzen Threadripper

    November 8, 2019 David Schor 0

    Random

    A Look At The Habana Inference And Training Neural Processors

    A Look At The Habana Inference And Training Neural Processors

    December 15, 2019 David Schor 3
    The RISC-V momentum continues with the GAP8, a new IoT/AI Application Processor

    The RISC-V momentum continues with the GAP8, a new IoT/AI Application Processor

    February 28, 2018 David Schor 0
    Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

    Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

    January 1, 2018 David Schor 2
    Analog AI Startup Mythic To Compute And Scale In Flash

    Analog AI Startup Mythic To Compute And Scale In Flash

    October 6, 2019 David Schor 0
    8th Gen Coffee Lake and 9th Gen Lineup

    8th Gen Coffee Lake and 9th Gen Lineup

    November 24, 2017 David Schor 0
    Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

    Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

    July 24, 2018 David Schor 0
    TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

    TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

    June 16, 2019 David Schor 6

    ARM WorldView All

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
    Roadmaps Server Processors 

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    Arm’s New Cortex-M55 Breathes Helium
    Architectures Embedded Processors 

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
    Arm Unveils the Cortex-A78: When Less Is More
    Architectures Mobile Processors 

    Arm Unveils the Cortex-A78: When Less Is More

    May 26, 2020 David Schor 0
    Arm Cortex-X1: The First From The Cortex-X Custom Program
    Architectures Mobile Processors 

    Arm Cortex-X1: The First From The Cortex-X Custom Program

    May 26, 2020 David Schor 0
    Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55
    Architectures Neural Processors 

    Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

    February 10, 2020 David Schor 0
    Arm Ethos is for Ubiquitous AI At the Edge
    Architectures Linley Processor Conference Neural Processors 

    Arm Ethos is for Ubiquitous AI At the Edge

    February 6, 2020 David Schor 0

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