Architectures

Analog AI Startup Mythic To Compute And Scale In Flash

David SchorArchitectures, Neural ProcessorsOctober 6, 2019 Tagged 40 nm, AI, analog, eFlash, embedded flash, Mythic, neural processors, RISC-V

A look at the IPU architecture of analog AI startup Mythic which attempts to significantly reduce the power consumption by computing directly in analog in flash.

Pages: 1 2

Alibaba Launches DC Inference Accelerators

David SchorArchitectures, Neural ProcessorsSeptember 28, 2019 Tagged 12nm, AI, Ali-NPU, Alibaba, Hanguang, Hanguang 800, neural processors, Wujian, Xuantie

Alibaba launches its own homegrown inference accelerator for their own cloud.

Inside Tesla’s Neural Processor In The FSD Chip

David SchorArchitectures, Hot Chips 31, Neural ProcessorsSeptember 22, 2019 Tagged 14 nm, FSD Chip, Full Self-Driving Chip, Hot Chips, Hot Chips 31, neural processors, self-driving, Tesla

A deep dive into the custom-designed Tesla neural processing units integrated inside the company’s full self-driving (FSD) chip based on the Tesla Hot Chips 31 talk.

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

David SchorArchitectures, Interconnects, Packaging, Process TechnologiesSeptember 21, 2019 Tagged 12LP, 12nm, 3D packaging, ARM, design-for-test, GlobalFoundries, hybrid bonding

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

David SchorArchitectures, Server ProcessorsSeptember 14, 2019 Tagged 14 nm, 14HP, IBM, z/Architecture, z15

IBM introduces its latest Z mainframe, the z15. Here’s a detailed look at the changes and enhancements that were made including the new system architecture and CPU microarchitecture.

Pages: 1 2

IBM Open Sources Power ISA, Delays POWER10 to 2021

David SchorArchitectures, OpenPOWER Summit, Roadmaps, Server ProcessorsSeptember 12, 2019 Tagged IBM, OpenPOWER, OpenPOWER Summit, OpenPOWER Summit 2019, POWER, POWER10, POWER9, PowerAXON

At the recent OpenPOWER Summit, IBM outlined their new roadmap, open-sourced the Power ISA, and made a number of additional announcements.

A Look At The Ice Lake Thunderbolt 3 Integration

David SchorArchitectures, InterconnectsAugust 11, 2019 Tagged 10nm, Ice Lake, Thunderbolt, Thunderbolt 3, USB 3.1, USB 4, x86

At look the Ice Lake Thunderbolt 3 integration, Intel’s biggest integration since the graphics on Sandy Bridge.

DARPA ERI: HIVE and Intel PUMA Graph Processor

David SchorArchitectures, ERI Summit 2019, Server ProcessorsAugust 4, 2019 Tagged DARPA, DARPA HIVE, Graph Processor, Intel PUMA, Programmable Unified Memory Architecture, PUMA

An update on the DAPRA HIVE program and the first disclosure of Intel’s Graph Analytics (GA) processor that is currently under development

DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

David SchorArchitectures, Circuit Design, ERI Summit 2019, FPGAsJuly 20, 2019 Tagged AIB, Ayar Labs, chiplet, DARPA, EMIB, ERI Summit, ERI Summit 2019, FPGA, GlobalFoundries, Photonics, RISC-V

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

A Look At The AMD Zen 2 Core

David SchorArchitecturesJuly 6, 2019 Tagged 7nm, branch prediction, x86, Zen, Zen 2

Ahead of the highly anticipated Ryzen 3000 desktop series launch, here is a look at the AMD Zen 2 core microarchitecture.

Pages: 1 2