Architectures

Arm Unveils the Cortex-A78: When Less Is More

Architectures Mobile Processors May 26, 2020 0

Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.

Arm Cortex-X1: The First From The Cortex-X Custom Program

Architectures Mobile Processors May 26, 2020 0

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new Cortex-X Custom Program.

NEC Readies 2nd Gen Vector Engine

Architectures Vector Processors May 15, 2020 0

NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

Architectures Hot Chips 31 IEDM 2019 ISSCC 2020 April 5, 2020 1

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

Architectures Circuit Design ISSCC 2020 March 8, 2020 5

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors March 1, 2020 0

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Radeon RX 5700: Navi and the RDNA Architecture

Architectures Circuit Design Graphics Processors ISSCC 2020 February 23, 2020 1

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

Architectures Floorplanning Interconnects ISSCC 2020 February 21, 2020 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

Architectures Neural Processors February 10, 2020 0

Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an ultra-low-power dedicated NPU for embedded applications.

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

Architectures Hot Interconnects 26 Interconnects Supercomputers February 9, 2020 0

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.