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Thursday, April 22, 2021
Latest:
  • Intel Launches 3rd Gen Ice Lake Xeon Scalable
  • Arm Highlights Near-Term Roadmap
  • Arm Launches ARMv9
  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
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Architectures

Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021April 6, 2021 David Schor 1 Comment 10nm, AVX-512, Ice Lake, Intel, Sunny Cove, x86, Xeon Gold, Xeon Platinum, Xeon Scalable, Xeon Silver

Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

Read more
Architectures Roadmaps 

Arm Launches ARMv9

March 30, 2021March 30, 2021 David Schor 3 Comments ARM, ARMv8, ARMv9, Confidential Compute Architecture (CCA), Scalable Vector Extension (SVE), Scalable Vector Extension 2 (SVE2)

Ten years after launching ARMv8, Arm is launching the ARMv9 architecture for the next decade of compute.

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Architectures 

The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

June 29, 2020September 19, 2020 David Schor 10 Comments Advanced Matrix Extension (AMX), AI, Intel, matrices, Sapphire Rapids, x86

Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.

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Architectures Embedded Processors 

Arm’s New Cortex-M55 Breathes Helium

June 20, 2020 David Schor 0 Comments AI, ARM, ARMv8, Cortex, Cortex-M, Cortex-M55, Helium, M-Profile Vector Extension (MVE)

A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.

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Architectures Mobile Processors 

Arm Unveils the Cortex-A78: When Less Is More

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A77, Cortex-A78

Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.

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Architectures Mobile Processors 

Arm Cortex-X1: The First From The Cortex-X Custom Program

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A78, Cortex-X, Cortex-X1

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new Cortex-X Custom Program.

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Architectures Vector Processors 

NEC Readies 2nd Gen Vector Engine

May 15, 2020 David Schor 0 Comments NEC, SX series, SX-Aurora, Vector Engine (VE), vector processors

NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.

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Architectures Hot Chips 31 IEDM 2019 ISSCC 2020 

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020 David Schor 1 Comment 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

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Architectures Circuit Design ISSCC 2020 

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020 David Schor 5 Comments 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

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Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors 

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020 David Schor 0 Comments 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

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  • ← Previous

Top Six Articles

  • TSMC Details 5 nm
  • IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects
  • Arm Launches ARMv9
  • IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32
  • Intel Launches 3rd Gen Ice Lake Xeon Scalable
  • TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

Recent

  • Intel Launches 3rd Gen Ice Lake Xeon Scalable

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1
  • Arm Highlights Near-Term Roadmap

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
  • Arm Launches ARMv9

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
  • Arm’s New Cortex-M55 Breathes Helium

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
  • Comment
  • Recent
  • JayN says:

    Interesting addition of avx512 IFMA. A 2018 artic...

  • Briny says:

    Given how often secure architectures have been bro...

  • Piotr says:

    Will SVE2 be mandatory in ARMv9 or not?...

  • Asd says:

    A popup asked me to comment, so here's a comment!...

  • Not Ludwig says:

    Intel has already canceled this chip so it doesn't...

  • Intel Launches 3rd Gen Ice Lake Xeon Scalable

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1
    Arm Highlights Near-Term Roadmap

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
    Arm Launches ARMv9

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10

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    Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges

    Japan cancels contract, kicks out 4th fastest supercomputer amid fraud charges

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    AMD Launches Ryzen Pro 4000 Series

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    ISSCC 2018: The IBM z14 Microprocessor And System Control Design

    May 13, 2018 David Schor 5

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    x86 WorldView All

    Intel Launches 3rd Gen Ice Lake Xeon Scalable
    Architectures Server Processors 

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1

    Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
    Architectures 

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
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    Architectures Neural Processors Server Processors 

    Centaur New x86 Server Processor Packs an AI Punch

    January 24, 2020 David Schor 3
    Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs
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    Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

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    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512
    Architectures Embedded Processors Neural Processors Server Processors 

    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

    December 9, 2019 David Schor 3
    SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
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    SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

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    Random

    Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

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    Intel Labs Builds A Neuromorphic System With 64 To 768 Loihi Chips: 8 Million To 100 Million Neurons

    Intel Labs Builds A Neuromorphic System With 64 To 768 Loihi Chips: 8 Million To 100 Million Neurons

    July 15, 2019 David Schor 0
    Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

    Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

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    Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

    Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

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    Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

    Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

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    AMD Launches Ryzen PRO 3000 Series

    AMD Launches Ryzen PRO 3000 Series

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    Intel, AMD Add New Mobile Pro Processors

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    ARM WorldView All

    Arm Highlights Near-Term Roadmap
    Roadmaps 

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
    Arm Launches ARMv9
    Architectures Roadmaps 

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
    Roadmaps Server Processors 

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    Arm’s New Cortex-M55 Breathes Helium
    Architectures Embedded Processors 

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
    Arm Unveils the Cortex-A78: When Less Is More
    Architectures Mobile Processors 

    Arm Unveils the Cortex-A78: When Less Is More

    May 26, 2020 David Schor 0
    Arm Cortex-X1: The First From The Cortex-X Custom Program
    Architectures Mobile Processors 

    Arm Cortex-X1: The First From The Cortex-X Custom Program

    May 26, 2020 David Schor 0

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