Architectures

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

Architectures Neural Processors Supercomputers Supercomputing 19 November 24, 2019 0

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).

Samsung M5 Core Details Show Up

Architectures Mobile Processors November 21, 2019 0

Samsung details the high-level changes to the Exynos M5 core found in the Exynos 990.

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 November 17, 2019 1

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

Architectures Hot Chips 31 Interconnects Neural Processors Packaging November 16, 2019 0

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

Groq Tensor Streaming Processor Delivers 1 PetaOPS of Compute

Architectures November 15, 2019 0

AI startup Groq makes an initial disclosure of their Tensor Streaming Processor (TSP); a single chip capable of 1 petaOPS or 250 teraFLOPS of compute.

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

Architectures Hot Chips 31 Linley Processor Conference Neural Processors November 10, 2019 1

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

Architectures Hot Chips 31 Interconnects Server Processors November 3, 2019 0

IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.

Intel Unveils the Tremont Microarchitecture: Going After ST Performance

Architectures October 24, 2019 3

Intel unveils the Tremont microarchitecture, its next-generation low-power small x86 core.

Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator

Architectures Hot Chips 31 Neural Processors October 20, 2019 5

First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.

Analog AI Startup Mythic To Compute And Scale In Flash

Architectures Neural Processors October 6, 2019 0

A look at the IPU architecture of analog AI startup Mythic which attempts to significantly reduce the power consumption by computing directly in analog in flash.