Architectures

A Look At Qualcomm’s Data Center Inference Accelerator

September 12, 2021September 13, 2021 David Schor 7 nm, Cloud AI 100, Hot Chips, Hot Chips 33, Linley Processor Conference, neural processors, Qualcomm

A look at Qualcomm’s Data Center Inference Accelerator, the Cloud AI 100.

Architectures Data Processing Unit Subscriber Only Content

YouTube Accelerates Transcoding

August 21, 2021August 21, 2021 David Schor accelerator, ASPLOS 2021, google, H.264, subscriber only (general), video acceleration, Video Coding Unit (VCU), VP9, YouTube

Google accelerates YouTube and other video services with custom silicon.

Architectures Server Processors

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor Advanced Matrix Extension (AMX), AVX-512, Golden Cove, Intel, Intel 7, Sapphire Rapids, x86

Intel unveiled Sapphire Rapids, its next-generation server CPUs

Architectures Data Processing Unit Desktop Processors Mobile Processors

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor Alder Lake, Gracemont, Intel, Intel 7, Tremont, x86

Intel’s Gracemont small core eclipses last-generation Skylake big core performance and energy efficiency

Architectures Desktop Processors Mobile Processors

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor Alder Lake, DDR5, Golden Cove, Gracemont, Intel, Intel 7, LPDDR5x, PCIe 5.0, x86

Intel unveiled Alder Lake, the company’s next-generation mainstream heterogeneous multi-core SoC for mobile through desktop

Architectures Desktop Processors Mobile Processors Server Processors

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor Alder Lake, Golden Cove, Intel, Intel 7, Sapphire Rapids, x86

Intel details Golden Cove, the company’s next-generation big core for client and server SoCs

Architectures Manycore Processors

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI

July 10, 2021August 2, 2021 David Schor 7 nm, Esperanto, ET-Maxion, ET-Minion, ET-SoC-1, neural processors, RISC-V, TSMC

A look at Esperanto’s ET-SoC-1, the startup’s first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.

Architectures

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor ARM, ARMv9, ARMv9.2, Confidential Compute Architecture (CCA), confidential computing, Dynamic TrustZone, Realm Management Extension (RME), secure enclave, TrustZone

Arm introduces its Confidential Compute Architecture (CCA) which provides a mechanism for Realms, secure enclaves that may be used by any application in order to protect data in use from everything else on the system.

Architectures FPGAs Subscriber Only Content

Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

June 13, 2021June 13, 2021 David Schor 16 nm, Diamond Mesa, eASIC Nextreme, Intel, Intel eASIC, Structured ASIC, subscriber only (general)

With Intel’s acquisition of eASIC in 2018, the company’s latest product – codenamed Diamond Mesa – attempts to bridge the gap between full ASIC and FPGAs.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

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