Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
ArchitecturesNeural ProcessorsSupercomputersSupercomputing 19 November 24, 2019 0
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).
Read moreSamsung M5 Core Details Show Up
ArchitecturesMobile Processors November 21, 2019 0
Samsung details the high-level changes to the Exynos M5 core found in the Exynos 990.
Read moreSC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
ArchitecturesRoadmapsServer ProcessorsSupercomputersSupercomputing 19 November 17, 2019 1
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.
Read moreA Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
ArchitecturesHot Chips 31InterconnectsNeural ProcessorsPackaging November 16, 2019 0
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.
Read moreGroq Tensor Streaming Processor Delivers 1 PetaOPS of Compute
Architectures November 15, 2019 0
AI startup Groq makes an initial disclosure of their Tensor Streaming Processor (TSP); a single chip capable of 1 petaOPS or 250 teraFLOPS of compute.
Read moreA Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
ArchitecturesHot Chips 31Linley Processor ConferenceNeural Processors November 10, 2019 1
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
Read moreIBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface
ArchitecturesHot Chips 31InterconnectsServer Processors November 3, 2019 0
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.
Read moreIntel Unveils the Tremont Microarchitecture: Going After ST Performance
Architectures October 24, 2019 3
Intel unveils the Tremont microarchitecture, its next-generation low-power small x86 core.
Read moreIntel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
ArchitecturesHot Chips 31Neural Processors October 20, 2019 5
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data center inference accelerator.
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