Architectures

Ayar Labs Realizes Co-Packaged Silicon Photonics

Architectures Circuit Design Hot Chips 31 Interconnects Packaging January 19, 2020 0

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

Architectures Circuit Design Manycore Processors Network-on-Chip Neural Processors VLSI 2019 January 12, 2020 0

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered accelerator.

A Look At The Habana Inference And Training Neural Processors

Architectures Hot Chips 31 Neural Processors December 15, 2019 2

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Architectures Embedded Processors Neural Processors Server Processors December 9, 2019 2

Centaur lifts the veil on CNS, its next-generation x86 core for data center and edge computing. The core improving performance in many areas and adds support for the AVX-512 extension.

Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip

Architectures Neural Processors Supercomputers Supercomputing 19 November 24, 2019 0

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS as well as a supercomputer with a peak performance of 2 exaFLOPS (HP).

Samsung M5 Core Details Show Up

Architectures Mobile Processors November 21, 2019 0

Samsung details the high-level changes to the Exynos M5 core found in the Exynos 990.

SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Architectures Roadmaps Server Processors Supercomputers Supercomputing 19 November 17, 2019 1

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

Architectures Hot Chips 31 Interconnects Neural Processors Packaging November 16, 2019 0

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

Groq Tensor Streaming Processor Delivers 1 PetaOPS of Compute

Architectures November 15, 2019 0

AI startup Groq makes an initial disclosure of their Tensor Streaming Processor (TSP); a single chip capable of 1 petaOPS or 250 teraFLOPS of compute.

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

Architectures Hot Chips 31 Linley Processor Conference Neural Processors November 10, 2019 1

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.