Architectures

The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

June 29, 2020September 19, 2020 David Schor 8 Comments Advanced Matrix Extension (AMX), AI, Intel, matrices, Sapphire Rapids, x86

Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids that introduces a new matrix register file and accompanying matrix operations.

Architectures Embedded Processors

Arm’s New Cortex-M55 Breathes Helium

June 20, 2020 David Schor 0 Comments AI, ARM, ARMv8, Cortex, Cortex-M, Cortex-M55, Helium, M-Profile Vector Extension (MVE)

A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.

Architectures Mobile Processors

Arm Unveils the Cortex-A78: When Less Is More

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A77, Cortex-A78

Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.

Architectures Mobile Processors

Arm Cortex-X1: The First From The Cortex-X Custom Program

May 26, 2020 David Schor 0 Comments 5 nm, ARM, ARMv8.2, Cortex, Cortex-A78, Cortex-X, Cortex-X1

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new Cortex-X Custom Program.

Architectures Vector Processors

NEC Readies 2nd Gen Vector Engine

May 15, 2020 David Schor 0 Comments NEC, SX series, SX-Aurora, Vector Engine (VE), vector processors

NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.

Architectures Hot Chips 31 IEDM 2019 ISSCC 2020

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020 David Schor 1 Comment 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Architectures Circuit Design ISSCC 2020

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020 David Schor 5 Comments 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020 David Schor 0 Comments 28nm, 65 nm, active interposer, CEA-Leti, chiplet, interconnects, interposer, ISSCC, ISSCC 2020, multi-chip package, STMicroelectronics

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Architectures Circuit Design Graphics Processors ISSCC 2020

Radeon RX 5700: Navi and the RDNA Architecture

February 23, 2020 David Schor 1 Comment 7 nm, AMD, ISSCC, ISSCC 2020, N7P, Navi, Radeon, Radeon RX 5700

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020 David Schor 2 Comments 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

← Previous