Architectures

Intel Discloses 9th Gen Core, Refreshes Core X, And Reintroduces STIM

David SchorArchitectures, Desktop ProcessorsOctober 14, 2018 Tagged 14nm, CFL-R, Coffee Lake, Core i5, Core i7, Core i9, Core X, Intel, Skylake, Skylake-X, Xeon W

An overview of Intel’s 9th Gen Core, new Core X processors, and the switch to STIM as well as a look at their transition from a mainstream quad-core to an octa-core.

Pages: 1 2

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

David SchorArchitectures, Floorplanning, Hot Chips 30, Interconnects, Server ProcessorsOctober 7, 2018 Tagged 14HP, 14nm, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

BrainChip Discloses Akida, A Neuromorphic SoC

David SchorArchitectures, Embedded Processors, Server ProcessorsSeptember 28, 2018 Tagged AI, Akida, BrainChip, neural processors, neuromorphic chip, spiking neural network

BrainChip discloses Akida, a Neuromorphic System-on-Chip for the edge and server.

Hot Chips 30: Nvidia Xavier SoC

David SchorArchitectures, Floorplanning, Hot Chips 30September 8, 2018 Tagged 12FFN, 12nm, AI, ARM, ARMv8, neural processors, Nvidia, NVLink, Tegra, Xavier

An overview of the Xavier SoC which was detailed by Nvidia at Hot Chips 30.

Hot Chips 30: AMD Raven Ridge

David SchorArchitectures, Circuit Design, Hot Chips 30August 26, 2018 Tagged 14LPP, 14nm, AMD, AMD's infinity fabric, APU, Hot Chips, Hot Chips 30, Radeon Vega, Raven Ridge, Vega, x86, Zen

Overview of AMD Raven Ridge APUs that were recently detailed at Hot Chips 30.

Pages: 1 2 3

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

Pages: 1 2 3

A look at Nvidia’s NVLink interconnect and the NVSwitch

David SchorArchitectures, Circuit Design, Conferences, Floorplanning, Graphics ProcessorsMay 6, 2018 Tagged 12FFN, 12nm, AI, DGX-1, DGX-2, GPU, Interconnect, Nvidia, NVLink, NVSwitch, Pascal, Volta

A look at Nvidia’s NVLink interconnect and the 2-billion transistor NVSwitch that is powering Nvidia’s latest DGX-2 deep learning machine.

QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

David SchorArchitectures, Circuit Design, ISSCC 2018, Neural ProcessorsApril 25, 2018 Tagged 3D packaging, 40 nm, 40LP, AI, die stacking, Hokkaido University, ISSCC, ISSCC 2018, Keio University, process technology, TCI, ThruChip Interface, TSMC, TSV

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

AMD’s Zen CPU Complex, Cache, and SMU

David SchorArchitectures, Circuit Design, ISSCC 2018April 18, 2018 Tagged 14LPP, 14nm, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

Pages: 1 2

Intel discloses Tremont, a Goldmont Plus successor

David SchorArchitecturesApril 4, 2018 Tagged 10nm, Atom, Intel, Tremont, x86

Intel has disclosed a new “Tremont” microarchitecture along with the release of their latest architecture ISA programming reference.