Skip to content
Monday, January 30, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

Power ISA

Hot Chips 32 Server Processors 

IBM Releases Power ISA v3.1; To Present POWER10 At Hot Chips 32

May 23, 2020May 23, 2021 David Schor bfloat16, Hot Chips, Hot Chips 32, IBM, OpenPOWER, POWER, Power ISA, POWER10

IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including 4-bit integers, and new instruction prefixes. IBM plans on presenting POWER10 at Hot Chips 32.

Read more
Architectures Hot Chips 31 Interconnects Server Processors 

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

November 3, 2019May 25, 2021 David Schor Centaur (buffer chip), Hot Chips 31, IBM, NVLink, Open Memory Interface (OMI), open source, OpenCAPI, Power ISA, POWER9

IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.

Read more
Architectures OpenPOWER Summit Roadmaps Server Processors 

IBM Open Sources Power ISA, Delays POWER10 to 2021

September 12, 2019May 25, 2021 David Schor IBM, OpenPOWER, OpenPOWER Summit, OpenPOWER Summit 2019, POWER, Power ISA, POWER10, POWER9, PowerAXON

At the recent OpenPOWER Summit, IBM outlined their new roadmap, open-sourced the Power ISA, and made a number of additional announcements.

Read more
Foundries Process Technologies Roadmaps Server Processors 

IBM Chooses Samsung 7nm EUV for Next-Gen POWER and Z Microprocessors

December 20, 2018May 25, 2021 David Schor 7LPP, 7nm, Common Platform Alliance, EUV, IBM, POWER, Power ISA, POWER10, Samsung, Z

IBM partners up with Samsung 7nm EUV process for their next-generation of POWER and Z microprocessors.

Read more
Architectures Floorplanning Hot Chips 30 Interconnects Server Processors 

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

October 7, 2018May 25, 2021 David Schor 14 nm, 14HP, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, Power ISA, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

Read more
Supercomputers 

ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest

June 16, 2018May 25, 2021 David Schor DoE, IBM, Nvidia, NVLink, ORNL, PCIe 4.0, POWER, Power ISA, Supercomputer

A look at the 200-petaFLOPS Summit supercomputer which was officially unveiled last Friday by Oak Ridge National Laboratory (ORNL).

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • A Look At AMD’s 3D-Stacked V-Cache
  • Intel Unveils Foveros Omni And Foveros Direct; Leveraging Hybrid Bonding
  • Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Intel Launches 12th Gen Core Desktop Alder Lake Processors

Intel Launches 12th Gen Core Desktop Alder Lake Processors

October 27, 2021November 3, 2021 David Schor
GlobalFoundries 14HP process, a marriage of two technologies

GlobalFoundries 14HP process, a marriage of two technologies

March 2, 2018May 25, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor
Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

October 7, 2022October 7, 2022 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

November 1, 2022November 2, 2022 David Schor
Reincarnating The 6502 Using Flexible TFT Tech For IoT

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020May 23, 2021 David Schor
VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

July 22, 2018May 25, 2021 David Schor
Ampere Ships First Gen ARM Server Processors

Ampere Ships First Gen ARM Server Processors

September 19, 2018May 25, 2021 David Schor
Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp

Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp

July 26, 2021July 26, 2021 David Schor
Arm’s New Cortex-M55 Breathes Helium

Arm’s New Cortex-M55 Breathes Helium

June 20, 2020May 23, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.