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Friday, October 7, 2022
Latest:
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency
  • The NPU Inside Every Intel PC
  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators
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X-Bus

Architectures Floorplanning Hot Chips 30 Interconnects Server Processors 

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

October 7, 2018May 25, 2021 David Schor 14 nm, 14HP, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, Power ISA, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

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Architectures Circuit Design Floorplanning ISSCC 2018 Server Processors 

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

May 13, 2018May 25, 2021 David Schor 14 nm, 14HP, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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Top Six Articles

  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • A Look At Intel 4 Process Technology
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency
  • Arm Unveils the Cortex-A78: When Less Is More
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

Recent

  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor
  • The NPU Inside Every Intel PC

    The NPU Inside Every Intel PC

    September 30, 2022September 30, 2022 David Schor
  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    September 20, 2022September 20, 2022 David Schor
  • N3E Replaces N3; Comes In Many Flavors

    N3E Replaces N3; Comes In Many Flavors

    September 4, 2022September 4, 2022 David Schor

Random Picks

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020May 25, 2021 David Schor
Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

May 12, 2019May 25, 2021 David Schor
Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

January 1, 2018May 25, 2021 David Schor
Inside Tesla’s Neural Processor In The FSD Chip

Inside Tesla’s Neural Processor In The FSD Chip

September 22, 2019July 11, 2021 David Schor
Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

December 23, 2018May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

September 14, 2019May 25, 2021 David Schor
Cavium Takes ARM to Petascale with Astra

Cavium Takes ARM to Petascale with Astra

August 25, 2018May 25, 2021 David Schor
Arm Targets Data Centers with New Roadmaps, Architectures, and Standards

Arm Targets Data Centers with New Roadmaps, Architectures, and Standards

December 16, 2018May 25, 2021 David Schor
A Look At Qualcomm’s Data Center Inference Accelerator

A Look At Qualcomm’s Data Center Inference Accelerator

September 12, 2021September 13, 2021 David Schor
TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor
AMD launches EPYC Embedded 3000 and Ryzen Embedded V1000 SoCs

AMD launches EPYC Embedded 3000 and Ryzen Embedded V1000 SoCs

February 23, 2018May 25, 2021 David Schor
POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

October 7, 2018May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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