X-Bus – WikiChip Fuse

POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

David SchorArchitectures, Floorplanning, Hot Chips 30, Interconnects, Server ProcessorsOctober 7, 2018 Tagged 14HP, 14nm, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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