WikiChip Fuse
ISSCC 2018: The IBM z14 Microprocessor And System Control Design

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

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AMD’s Zen CPU Complex, Cache, and SMU

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

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ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor

In recent years, IoT devices have been plagued with security issues. Memory and energy constraints of those low-power devices mean there is very little headroom for complex security implementations. At ISSCC 2018, a team of MIT researchers has attempted to address this problem with their low-power fully in-hardware crypto engine IoT RISC-V processor.

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ISSCC 2018: Intel’s Skylake-SP Mesh and  Floorplan

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

At IEDM 2017 and ISSCC 2018 Intel detailed their upcoming 10nm node, an aggressively scaled 7nm-class process technology that features new scaling accelerators as well as cobalt interconnect for the first time in high-volume manufacturing.

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