Floorplanning

Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

David SchorArchitectures, Floorplanning, Mobile ProcessorsMay 12, 2019 Tagged 10nm, 7nm, AVX-512, Gen11, Ice Lake, Sapphire Rapids, Tiger Lake

A look at Ice Lake mobile CPUs which bring a new CPU core, a new Gen11 GPU, and a new 4th Gen IPU as well the new roadmap detailed by Intel at their recent investor meeting which includes Xeon Sapphire Rapids CPUs and 7nm Xe Data Center GPGPUs for 2021.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

David SchorArchitectures, Floorplanning, Hot Chips 30, Interconnects, Server ProcessorsOctober 7, 2018 Tagged 14HP, 14nm, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

Hot Chips 30: Nvidia Xavier SoC

David SchorArchitectures, Floorplanning, Hot Chips 30September 8, 2018 Tagged 12FFN, 12nm, AI, ARM, ARMv8, neural processors, Nvidia, NVLink, Tegra, Xavier

An overview of the Xavier SoC which was detailed by Nvidia at Hot Chips 30.

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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A look at Nvidia’s NVLink interconnect and the NVSwitch

David SchorArchitectures, Circuit Design, Conferences, Floorplanning, Graphics ProcessorsMay 6, 2018 Tagged 12FFN, 12nm, AI, DGX-1, DGX-2, GPU, Interconnect, Nvidia, NVLink, NVSwitch, Pascal, Volta

A look at Nvidia’s NVLink interconnect and the 2-billion transistor NVSwitch that is powering Nvidia’s latest DGX-2 deep learning machine.

ISSCC 2018: AMD’s Zeppelin; Multi-chip routing and packaging

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 24, 2018 Tagged 14nm, 2D packaging, AMD, AMD's infinity fabric, EPYC, multi-chip package, Ryzen, x86, Zen

A look at AMD’s Zeppelin SoC and the Infinity Fabric, a multi-chip architecture used by AMD to scale their SoC design from the mainstream PC market all the way to the server market.

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ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 9, 2018 Tagged 14nm, floorplan, Intel, ISSCC, ISSCC 2018, Skylake, Skylake-SP, x86, Xeon Scalable

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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