The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
Architectures Jun 29, 2020 7
Intel publishes details of its upcoming Advanced Matrix Extension (AMX), an x86 extension set to debut with Sapphire Rapids...
Arm’s New Cortex-M55 Breathes Helium
Architectures Jun 20, 2020 0
A look at the new Cortex-M55, an embedded ARMv8 core with the new Helium vector extension.
Arm Unveils the Cortex-A78: When Less Is More
Architectures May 26, 2020 0
Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.
Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new...
NEC Readies 2nd Gen Vector Engine
Architectures May 15, 2020 0
NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
Architectures Apr 5, 2020 1
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality
Interconnects May 17, 2020 3
A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel's EMIB (2.5D)...
TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key...
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The...
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
Architectures Feb 9, 2020 0
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Architectures Nov 24, 2019 0
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Architectures Nov 17, 2019 1
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...
Conference Coverage
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Process Technologies Oct 18, 2019 0
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
Architectures Apr 5, 2020 1
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
Architectures Apr 5, 2020 1
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including...
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC
Architectures Apr 5, 2020 1
A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
Architectures Nov 10, 2019 1
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
Top 6 Trending
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The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
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TSMC Details 5 nm
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TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter
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Arm’s New Cortex-M55 Breathes Helium
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VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension
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IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects
