WikiChip Fuse

Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End

David SchorArchitectures, Mobile ProcessorsJanuary 14, 2019 Tagged 8LPP, ARM, ARMv8, ARMv8.2, Exynos, Samsung

Samsung details the initial changes to the Exynos M4 core found in the Exynos 9820 which will be in Samsung’s next-generation Galaxy S10 smartphone.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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ARM Announces the Mali-C52 and Mali-C32 ISPs for Intelligent Vision Devices

David SchorImage Signal ProcessorJanuary 3, 2019 Tagged ARM, Iridix, ISP, Mali, Mali-C32, Mali-C52

Today, ARM is announcing two new image signal processors, the Mali-C52 and Mali-C32, in order to address customer demand for emerging intelligent vision devices.

Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

David SchorArchitectures, Desktop Processors, Roadmaps, Server ProcessorsDecember 23, 2018 Tagged 10nm, 7nm, AVX-512, Foveros, Golden Cove, Gracemont, Ice Lake, Palm Cove, Sunny Cove, Tremont, Willow Cove, x86

Last week Intel disclosed initial details of their next-generation core microarchitecture, Sunny Cove, which will make it into future Ice Lake client and server chips among other products.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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IBM Chooses Samsung 7nm EUV for Next-Gen POWER and Z Microprocessors

David SchorFoundries, Process Technologies, Roadmaps, Server ProcessorsDecember 20, 2018 Tagged 7LPP, 7nm, Common Platform Alliance, EUV, IBM, POWER, POWER10, Samsung, Z

IBM partners up with Samsung 7nm EUV process for their next-generation of POWER and Z microprocessors.

Arm Targets Data Centers with New Roadmaps, Architectures, and Standards

David SchorArchitectures, ARM TechCon 2018, Roadmaps, Server Processors, Supercomputing 18December 16, 2018 Tagged 5nm, 7nm, Ares, ARM, data center, neoverse, Poseidon, SBBR, SBSA, ServerReady, Zeus

Arm outlines server strategy with an ambitious plan to make a dent in the data center business that is dominated by Intel through standardization and a new roadmap with high-performance ‘server-class’ cores.

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A Look at NEC’s Latest Vector Processor, the SX-Aurora

David SchorArchitectures, Hot Chips 30, Server Processors, Supercomputing 18December 9, 2018 Tagged 16nm, 3D packaging, HBM2, interposer, multi-chip package, NEC, Packaging, SIMD, SX series, SX-Aurora, vector processors

A look at the NEC SX-Aurora, their latest vector processor – increasing compute while maintaining a high B/F through six HBM2 modules leveraging TSMC 2nd gen CoWoS technology. The SX-Aurora introduces a new form factor, system architecture, and execution model.

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AMD Discloses Initial Zen 2 Details

David SchorArchitectures, Server ProcessorsNovember 18, 2018 Tagged 14nm, 7nm, AMD, Rome, x86, Zen, Zen 2, Zen 4

Following AMD’s recent Zen 2 and Rome disclosure, here’s a look at what has changed and what second-generation EPYC brings to the table.

Intel Cascade Lake Brings Hardware Mitigations, AI Acceleration, SCM Support

David SchorArchitectures, Hot Chips 30, Server ProcessorsNovember 11, 2018 Tagged 14nm, AVX-512, AVX512VNNI, Cascade Lake, Cascade Lake AP, Cascade Lake SP, CSL, CSX, Intel, persistent memory, SCM, Skylake, storage-class memory, x86

A look at Cascade Lake, Intel’s microarchitecture for next-generation Xeon microprocessors featuring process enhancements, persistent memory support, and AI acceleration.

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