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TSMC Details 5 nm

Foundries Mar 21, 2020 0

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with a high-mobility channel and highest-density SRAM cells. Read more

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

Architectures Mar 8, 2020 5

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of... Read more

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

Interconnects Mar 3, 2020 0

TSMC announces an enhancement to its CoWoS packaging technology with support for up to... Read more

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

Architectures Mar 1, 2020 0

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six... Read more

Intel Refreshes 2nd Gen Xeon Scalable, Slashes Prices

Server Processors Feb 27, 2020 0

Intel refreshes its second-generation Xeon Scalable lineup mid-cycle with new mainstream dual-socket CPUs, improving... Read more
IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...
Radeon RX 5700: Navi and the RDNA Architecture
A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture...
7nm Boosted Zen 2 Capabilities but Doubled the Challenges
The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new...
Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55
Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the...
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The...
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
UMC Rolls Out 22-Nanometer
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
TSMC 5-Nanometer Update
An update on TSMC's upcoming 5-nanometer process technology.
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...

Conference Coverage

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
TSMC Details 5 nm
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...
Ayar Labs Realizes Co-Packaged Silicon Photonics
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A Look At The Habana Inference And Training Neural Processors
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface...
Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data...