WikiChip Fuse

Our latest coverage from the chip architecture world, including announced and planned as well as recently launched products.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

Architectures Interconnects Network-on-Chip

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor

Arm is introducing a new cache-coherent and SoC-level interconnects, the CoreLink CI-700 & NI-700.

Architectures Interconnects Mobile Processors

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor

Arm introduces its new DynamIQ Share Unit 110 for new Armv9 CPUs

Architectures Embedded Processors Mobile Processors

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

May 25, 2021May 25, 2021 David Schor

Arm launches the Cortex-X2, second-generation Cortex-X, and their new flagship performance Armv9 big core.

IEDM 2020 Interconnects Packaging Subscriber Only Content

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

Architectures Interconnects Network-on-Chip

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, cache coherency, CI-700, CMN-700, CoreLink, interconnects, Memory Tagging Extension (MTE), mesh interconnect, NI-700

Arm is introducing a new cache-coherent and SoC-level interconnects, the CoreLink CI-700 & NI-700.

Architectures Interconnects Mobile Processors

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, DSU-110, Memory Tagging Extension (MTE)

Arm introduces its new DynamIQ Share Unit 110 for new Armv9 CPUs

Architectures Embedded Processors Mobile Processors

Arm Launches Its New Flagship Performance Armv9 Core: Cortex-X2

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-X, Cortex-X2, Scalable Vector Extension 2 (SVE2)

Arm launches the Cortex-X2, second-generation Cortex-X, and their new flagship performance Armv9 big core.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

May 25, 2021May 26, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A510, Scalable Vector Extension 2 (SVE2)

Arm introduces their new Armv9 little core, the Cortex-A510 with significant PPA improvements.

Architectures Embedded Processors Mobile Processors

Arm Unveils Next-Gen Armv9 Big Core: Cortex-A710

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, Cortex-A, Cortex-A710, Scalable Vector Extension 2 (SVE2)

Arm unveils their newest Armv9 big core, the Cortex-A710.

Packaging Power Management Subscriber Only Content

The Magnets Under the Icy Lake

May 23, 2021May 23, 2021 David Schor 10 nm, Fully Integrated Voltage Regulator (FIVR), Ice Lake, subscriber only (general)

The magnets under the icy lake

Architectures Interconnects

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor ARM, CMN-600, CMN-700, DDR5, mesh interconnect, neoverse, Neoverse N, Neoverse V, PCIe 5.0

Arm’s CMN-700 is the company’s latest high-performance cache-coherent mesh interconnect for the server market, enabling SoC designs with twice as many cores, as much as half a GiB of cache, dozens of memory controllers, and support dozens of cache-coherent accelerators, chiplets, and processors.

Foundries IEDM 2020 Process Technologies Roadmaps Subscriber Only Content

Samsung Details 5nm and 4nm; Adds 8LPA, 5LPP, and 4LPP Nodes; Readies 3nm GAA For Next Year

May 21, 2021May 23, 2021 David Schor 3 nm, 4 nm, 4LPE, 4LPP, 5 nm, 5LPE, 5LPP, 7 nm, IEDM 2020, Samsung, Samsung Foundry, subscriber only (general)

Samsung revealed more details of its 5LPE process technology which recently ramped, gave a roadmap status update along with new stop-gap nodes announcement.

← Previous

Subscriber-Only Content

ArchitecturesView All

Process TechnologyView All

SupercomputersView All

ConferencesView All