IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...
Radeon RX 5700: Navi and the RDNA Architecture
Architectures Feb 23, 2020 1
A look at AMD's Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture...
The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new...
Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the...
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
Architectures Feb 9, 2020 0
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The...
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
TSMC 5-Nanometer Update
ARM TechCon 2019 Nov 1, 2019 0
An update on TSMC's upcoming 5-nanometer process technology.
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
Architectures Feb 9, 2020 0
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Architectures Nov 24, 2019 0
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Architectures Nov 17, 2019 1
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...
Conference Coverage
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Process Technologies Oct 18, 2019 0
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...
IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...
CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
Architectures Nov 10, 2019 1
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface...
Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
Architectures Oct 20, 2019 6
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data...
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