Intel Unveils the Tremont Microarchitecture: Going After ST Performance
Architectures Oct 24, 2019 3
Intel unveils the Tremont microarchitecture, its next-generation low-power small x86 core.
Samsung M5 Core Details Show Up
Architectures Nov 21, 2019 0
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
TSMC 5-Nanometer Update
ARM TechCon 2019 Nov 1, 2019 0
Samsung 5 nm and 4 nm Update
ARM TechCon 2019 Oct 19, 2019 3
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Architectures Nov 24, 2019 0
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Architectures Nov 17, 2019 1
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...
Cavium Takes ARM to Petascale with Astra
Supercomputers Aug 25, 2018 0
A look at the Astra supercomputer, the most powerful ARM-based supercomputer being built for Sandia National Labs.
Conference Coverage
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Process Technologies Oct 18, 2019 0
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here's a look at Intel's 10-nanometer standard...
A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system...
Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface...
AMD’s Zen CPU Complex, Cache, and SMU
Architectures Apr 18, 2018 0
A look at AMD's Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores...
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
Architectures Nov 10, 2019 1
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface...
Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
Architectures Oct 20, 2019 6
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data...
Top 6 Trending
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Ayar Labs Realizes Co-Packaged Silicon Photonics
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A Look At Celerity's Second-Gen 496-Core RISC-V Mesh NoC
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TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY
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TSMC Digs Trenches In Search Of Higher Performance
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Zhaoxin launches their highest-performance Chinese x86 chips
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TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
