WikiChip Fuse

Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55

Architectures Feb 10, 2020 0

Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the Ethos-U55, an ultra-low-power dedicated NPU for embedded applications. Read more

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

Architectures Feb 9, 2020 0

A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect... Read more

Arm Ethos is for Ubiquitous AI At the Edge

Architectures Feb 6, 2020 0

Arm's Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT... Read more

Intel Axes Nervana Just Two Months After Launch

Architectures Feb 3, 2020 4

Intel axes Nervana in favor of Habana. Read more

Centaur New x86 Server Processor Packs an AI Punch

Architectures Jan 24, 2020 3

A look at Centaur's new server-class x86 SoC with an integrated neural processor. Read more
Arm Launches the Cortex-M55 and Its MicroNPU Companion, the Ethos-U55
Arm launches two new IPs for deeply-embedded AI: the Cortex-M55 with the new M-Profile Vector Extension (Helium), and the...
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Arm Ethos is for Ubiquitous AI At the Edge
Arm's Ethos family takes aim at ubiquitous AI with NPUs for ultra-low power IoT to high-performance smartphones and AR/VR.
Intel Axes Nervana Just Two Months After Launch
Intel axes Nervana in favor of Habana.
Centaur New x86 Server Processor Packs an AI Punch
A look at Centaur's new server-class x86 SoC with an integrated neural processor.
Ayar Labs Realizes Co-Packaged Silicon Photonics
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
UMC Rolls Out 22-Nanometer
UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
TSMC 5-Nanometer Update
An update on TSMC's upcoming 5-nanometer process technology.
Samsung 5 nm and 4 nm Update
Update and analysis of Samsung's upcoming 5-nanometer and 4-nanometer process technologies.
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect
A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...
Japanese AI Startup Preferred Networks Designed A Custom Half-petaFLOPS Training Chip
Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...
SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...

Conference Coverage

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...
Intel Expands 22FFL With Production-Ready RRAM and MRAM on FinFET
Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.
TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging
An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.
TSMC Digs Trenches In Search Of Higher Performance
TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029
Intel's process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into...
IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery
Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here's a look at Intel's 10-nanometer standard...
ISSCC 2018: The IBM z14 Microprocessor And System Control Design
A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system...
QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor
Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface...
AMD’s Zen CPU Complex, Cache, and SMU
A look at AMD's Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores...
Ayar Labs Realizes Co-Packaged Silicon Photonics
Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...
A Look At The Habana Inference And Training Neural Processors
A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...
A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.
IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface
IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface...
Intel Spring Hill: Morphing Ice Lake SoC Into A Power-Efficient Data Center Inference Accelerator
First detailed at Hot Chips 31, Intel Spring Hill morphs the Ice Lake SoC into a highly power-efficient data...