Arm unveils the Cortex-A78 microarchitecture for next-generation flagship smartphones.

Arm launches the Cortex-X1, their most powerful Cortex CPU to date. This is the first CPU from the new...

NEC readies 2nd-generation Vector Engine, Type 20, offering higher memory bandwidth and a few more vector cores.

A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active...

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel's EMIB (2.5D)...

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key...

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The...

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...

UMC says it has started rolling out its 22-nanometer planar process, offering a new lower-power and cost-sensitive migration path...

A dive into the Rosetta ASIC switch, the engine behind Cray's new Slingshot interconnect powering the upcoming Shasta exascale...

Japanese AI Startup Preferred Networks has been working on a custom training chip with a peak performance of half-petaFLOPS...

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel's first Xe GPGPU for HPC,...

A look at the 496-core RISC-V manycore array, network-on-chip, and the digital PLL of the Celerity open-source RISC-V tiered...

Intel expands its 22FFL process with new production-ready MRAM and RRAM technologies.

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new,...

A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry's highest density transistors with...

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of...

IBM releases Power ISA v3.1. Among the new instructions, there is new bfloat16 support, new reduced-precision outer-product operations including...

A look at Lakefield, Intel's new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company...

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step...

A look at the Habana inference and training neural processors designed for the acceleration of data center workloads.

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI...

A look at the microarchitecture of Intel Nervana next-generation data center training neural processor, codename Spring Crest.