WikiChip Fuse
TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.

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TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

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Intel Axes Nervana Just Two Months After Launch

Intel axes Nervana in favor of Habana.

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Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.

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Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.

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NEC Refreshes SX-Aurora Vector Engine, Outlines Roadmap

NEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.

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SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio

Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.

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Marvell Lays Out ARM Server Roadmap

Marvell outlines its current and future Arm server microprocessor roadmap, aiming at a 2-year cadence with greater than 2x performance gen-over-gen.

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Samsung 5 nm and 4 nm Update

Update and analysis of Samsung’s upcoming 5-nanometer and 4-nanometer process technologies.

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IBM Open Sources Power ISA, Delays POWER10 to 2021

At the recent OpenPOWER Summit, IBM outlined their new roadmap, open-sourced the Power ISA, and made a number of additional announcements.

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