Your Chips and Semi News
Arm updates its Neoverse roadmap with the Neoverse N2 and V1, introducing SVE support for the first time as well as bfloat16 operations. Like the Cortex-X series, the Neoverse V-series will ease its power and area constraints in favor of higher performance.
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TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.
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TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.
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Intel axes Nervana in favor of Habana.
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Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.
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Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.
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NEC refreshes its SX-Aurora Vector Engine accelerator cards, adopts AMD processors, and outlines roadmap.
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Intel unveils the node architecture of the Aurora Supercomputer; the system will feature Intel’s first Xe GPGPU for HPC, 7nm Ponte Vecchio.
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Marvell outlines its current and future Arm server microprocessor roadmap, aiming at a 2-year cadence with greater than 2x performance gen-over-gen.
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Update and analysis of Samsung’s upcoming 5-nanometer and 4-nanometer process technologies.
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