TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

TSMC started mass production of their 7-nanometer node in April 2018. Since then we have seen a number of high-profile processors that make use of the technology including the Apple A12 and A12X, the Kirin 980, and soon Qualcomm’s Snapdragon 855 and AMD Zen 2.

7 nm

For TSMC, the 7-nanometer node is considered a full node shrink over their 16-nanometer. They did push out a 10-nanometer node but TSMC considers their 10 nm to be a short-lived node and was intended to serve as a learning steppingstone on their way to 7. In many ways, it’s comparable to Intel’s 10-nanometer and Samsung’s 7-nanometer nodes. Compared to their own 16-nanometer technology, 7 nm provides around 35-40% speed improvement or 65% lower power.


This is a fourth-generation FinFET, fifth-generation HKMG, gate-last, dual gate oxide process.

  • 4th generation FinFET
  • 5th generation high-K metal gate
  • 3.3x routed gate density
  • Cobalt contacts
  • SADP for critical layers

For the 7-nanometer process, deep ultraviolet (DUV) 193 nm ArF Immersion lithography continues to be used. The limitations of i193 dictated some of the design rules for the process as we’ll shortly show. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the SADP point. We want to point out that while at IEDM TSMC reported slightly more aggressive pitches, the numbers shown in this article are the actual pitches used in their standard cells (and the actual pitches you will find in the A12 and the SDM855).

TSMC Node Comparison
Node 16 nm 10 nm 7 nm 7nm/10nm Δ
Gate 90 nm 66 nm 57 nm 0.86x
Min Metal 64 nm 42 nm 40 nm 0.95x

The transistor profile has been enhanced as well. Like Intel, TSMC introduced cobalt fill at the trench contact, replacing the tungsten contact. This has the effect of reducing the resistance at that area by 50%. Some of the area scaling and cost benefits were achieved through fin pitch/height scaling. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and subthreshold slope (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I device delay is still better because the intrinsic capacitance like the Cgate and Cov still scale with Ieff.

Transistor Profile
Node 10 nm 7 nm Δ
Fin Pitch 36 nm 30 nm 0.83x
Fin Width 6 nm 6 nm 1.00x
Fin Height 42 nm 52 nm 1.24x

Another way to visualize the effect of the width and height scaling is through the effective width. In the graph below we plotted the effective width from TSMC 16 nanometer to the current 7-nanometer node.


Different multi-Vt devices were developed for this process with a Vt range of around 200 mV.

Design Rules

Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point.

7-nanometer Design Rules
Layer Pitch (nm) Patterning Notes
Fin 30 SAQP
Poly 57 SADP
M0 40 SADP Mx
M1 40 SADP 1x
M2 40 SADP 1x
M3 40 SADP 1x
M4 40 SADP 1x
M5 76 Single 1.9x
M6 76 Single 1.9x
M7 76 Single 1.9x
M8 76 Single 1.9x
M9 76 Single 1.9x
M10 124 Single 3.1x
M11, M12 720 Single 18x


One of the processors that are fabricated on TSMC 7-nanometer is Qualcomm’s Snapdragon 855. At the recent 2019 VLSI Symposium, Qualcomm and TSMC jointly presented a paper on the 7 nm process and some of the enhancements that were done on that chip. The processor was presented by Ming Cai, Principle Engineer and 7 nm process DTCO project lead at Qualcomm. Packaged in tiny 8.5 mm by 8.5 mm plastic case, fabricated on TSMC 7 nm and packing around 6.7 billion transistors, the Snapdragon 855 is Qualcomm’s latest flagship mobile SoC and 5G platform.

The Snapdragon 855 is also the first commercial 5G mobile platform. Qualcomm did not forget to highlight that their peak data rate of cellular modems has been increasing at a rate of ~2X per year for quite some time now with their first 5G modem exceeding 10 Gbps this year.

The Snapdragon 855 integrates eight CPU cores, their custom Adreno GPU, DPS with AI acceleration capable of over 7 TOPS, and various connectivity technologies.



TSMC 7-nanometer comes in two variations – low power and high performance. Those cells are 240 nm and 300 nm tall respectively.

7-Nanometer Flavors
Type Low Power High Performance
Fin Pitch 30 nm
Metal 40 nm (smallest pitch used with DP)
76 nm (smallest pitch used with SP)
Gate Pitch 57 nm 64 nm
Height 240 nm
8-fin x 30 nm
300 nm
10-fin x 30 nm
Tracks 6 T 7.5 T

Chi reported that on their own SoC, the high-performance cells deliver around 10-13% higher effective drive current (Ieff), albeit at the cost of being slightly leakier transistors.

The dense cells come at around 91.2 MTr/mm² while the less dense, high-performance cells, are calculated at around 65 MTr/mm².

Process Density Comparison

In terms of actual transistor footprint, the size is very similar to Intel. However, due to a number of cell-level optimizations, Intel edges out at around 10% higher cell-level density. It’s worth adding that Intel’s high-performance cells are also denser than TSMC’s 7nm HP cells with their ultra-high-performance cells being around 1% denser.


One of the things TSMC really has going for it on their 7 nm node is their SRAM density. Here, the 7-nanometer high-density SRAM bitcell is 0.027 µm², making it the second-densest cell reported to date. On the current FinFET processes, the bitcells are largely fin-quantized. TSMC enjoys very good scaling on their SRAM because of their aggressive fin pitch.

Depending on the consistency of the SoC, due to the high density of TSMC 7nm SRAM, leveraging a large amount of SRAM could be advantageous. On modern SoCs, especially mobile SoCs, the vast majority of the transistors go into various caches. We are already seeing some designs that are taking advantage of this such as AMD which has doubled the L3 size from 8 MiB to 16 MiB.

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1 year ago

Hello David, how can you say that:
” It’s worth adding that Intel’s high-performance cells are also denser than TSMC’s 7nm HP cells with only the ultra-high-performance cells being 1% less dense.”
and and the same time here:
we can see that intel UHP is 67,18 MTr/mm2 and TSMC HP 64,98 MTr/mm2comment image

can you explain this?

Reply to  David Schor
1 year ago

is it correct to assume that intel HP node will be in mobile chips and UHP in desktops in the future?

Reply to  David Schor
1 year ago

3,4% denser? 6718/64,98= 103,39%
sorry to be so picky 😀

7 months ago

The actual paper doesn’t seem to necessarily imply that the Prime core is in H300 vs H240 in the Gold. All it say is that they’re using CPP64 instead of CPP57 for the other cores, and given the area differential between the two it’s more likely that they both are using the same cell heights and only differ by the poly pitch, as otherwise there ought to be a much larger differential in size. That doesn’t rule out the possibility of both using H300, as the Qualcomm implementation of A76 is at 1.58mm^2 w/512kB L2 vs 1.30mm^2 w/512KB L2 for Hisilicon on the Kirin 980, so even the 256KB L2 Gold A76’s at 1.27mm^2 are almost the same size. Hard to suss out if there’s a library cell height difference or if it’s all down to Qualcomm’s customizations.

Also, the labeling of M0 as Mx is incorrect – M0 is a stdcell internal only layer, and Mx really refers to M2 and up. M1 isn’t at the same dimensions either – as evidenced by AMD’s ISSCC20 numbers. The VLSI paper just says that the minimal dual-patterned pitch is 40nm, not that all Mx layers are at the same dimension.

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