IEDM – WikiChip Fuse

Intel Talks 10nm DTCO, EUV Benefits

June 22, 2021August 2, 2021 David Schor 10 nm, 5 nm, 7 nm, EUV, IEDM, IEDM 2020, Intel, subscriber only (general)

Intel talks 10-nanometers DTCO and the benefits of EUV on their future 7 nm and 5 nm nodes.

IEDM 2020 Interconnects Packaging Subscriber Only Content

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

Circuit Design Floorplanning IEDM 2018 Process Technologies

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

IEDM 2017 ISSCC 2018 Process Technologies

IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

February 17, 2018May 25, 2021 David Schor 10nm, FinFET, IEDM, IEDM 2017, Intel, ISSCC, ISSCC 2018, process technology

At IEDM 2017 and ISSCC 2018 Intel detailed their upcoming 10nm node, an aggressively scaled 7nm-class process technology that features new scaling accelerators as well as cobalt interconnect for the first time in high-volume manufacturing.

IEDM 2017

IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology

February 3, 2018May 25, 2021 David Schor 3D packaging, CIS, CMOS image sensor, die stacking, IEDM, IEDM 2017, Sony, TSV

At the 2017 IEDM Sony presented their 3-layer stacked state-of-the-art CMOS image sensor (CIS) technology used to minimize rolling shutter distortions and greatly increase the read speed and thus fps through the use of DRAM for temporarily storing the pixel data.

IEDM 2017 Process Technologies

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

December 21, 2017May 25, 2021 David Schor 7LP, 7nm, AMD, EUV, FinFET, GlobalFoundries, IBM, IEDM, IEDM 2017, process technology, SADP, SAQP

At the 2017 IEDM GlobalFoundries detailed their 7nm Leading Performance (7LP) process, an aggressively scaled version of their 14nm process optimized for next-generation mobile, SoC, and high-performance applications.

IEDM 2017 Process Technologies

IEDM 2017: Intel details 22FFL, a relaxed 14nm process for foundry customers, targets mobile and RF apps

December 15, 2017May 25, 2021 David Schor 14 nm, 22 nm, 22FFL, ASIC, FinFET, IEDM, IEDM 2017, Intel, Intel Custom Foundry, Interconnect, process technology, Radio Frequency

At the 2017 IEDM Intel detailed their 22FFL process, a relaxed 14nm process for Intel’s custom foundry customers. 22FFL was optimized for mobile, IoT, and RF applications offering a cost competitive process with excellent performance and simple design rules.

IEDM 2017 Processors

IEDM 2017: AMD’s grand vision for the future of HPC

December 5, 2017May 25, 2021 David Schor 2.5D packaging, 3D packaging, AMD, HBM, IEDM, IEDM 2017, Moore's Law, Packaging

Capping off a great year, AMD CEO Lisa Su opening address at IEDM 2017 highlighted key challenges for the future, predicting a paradigm shift in the design of processors and systems that will deliver another decade of performance gains.