IEDM – WikiChip Fuse

IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

David SchorIEDM 2017, ISSCC 2018, Process TechnologiesFebruary 17, 2018 Tagged 10nm, FinFET, IEDM, IEDM 2017, Intel, ISSCC, ISSCC 2018, process technology

At IEDM 2017 and ISSCC 2018 Intel detailed their upcoming 10nm node, an aggressively scaled 7nm-class process technology that features new scaling accelerators as well as cobalt interconnect for the first time in high-volume manufacturing.

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IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology

David SchorIEDM 2017February 3, 2018 Tagged 3D packaging, CIS, CMOS image sensor, die stacking, IEDM, IEDM 2017, Sony, TSV

At the 2017 IEDM Sony presented their 3-layer stacked state-of-the-art CMOS image sensor (CIS) technology used to minimize rolling shutter distortions and greatly increase the read speed and thus fps through the use of DRAM for temporarily storing the pixel data.

IEDM 2017: GlobalFoundries 7nm process; Cobalt, EUV

David SchorIEDM 2017, Process TechnologiesDecember 21, 2017 Tagged 7LP, 7nm, AMD, EUV, FinFET, GlobalFoundries, IBM, IEDM, IEDM 2017, process technology, SADP, SAQP

At the 2017 IEDM GlobalFoundries detailed their 7nm Leading Performance (7LP) process, an aggressively scaled version of their 14nm process optimized for next-generation mobile, SoC, and high-performance applications.

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IEDM 2017: Intel details 22FFL, a relaxed 14nm process for foundry customers, targets mobile and RF apps

David SchorIEDM 2017, Process TechnologiesDecember 15, 2017 Tagged 14nm, 22FFL, 22nm, ASIC, FinFET, IEDM, IEDM 2017, Intel, Intel Custom Foundry, Interconnect, process technology, Radio Frequency

At the 2017 IEDM Intel detailed their 22FFL process, a relaxed 14nm process for Intel’s custom foundry customers. 22FFL was optimized for mobile, IoT, and RF applications offering a cost competitive process with excellent performance and simple design rules.

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IEDM 2017: AMD’s grand vision for the future of HPC

David SchorIEDM 2017, ProcessorsDecember 5, 2017 Tagged 2.5D packaging, 3D packaging, AMD, HBM, IEDM, IEDM 2017, Moore's Law, Packaging

Capping off a great year, AMD CEO Lisa Su opening address at IEDM 2017 highlighted key challenges for the future, predicting a paradigm shift in the design of processors and systems that will deliver another decade of performance gains.

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