12LP – WikiChip Fuse

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Interconnects Packaging Process Technologies

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

September 21, 2019June 11, 2021 David Schor 12LP, 12nm, 3D packaging, ARM, CMN-600, design-for-test, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, Trishul (Arm test chip)

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

Desktop Processors

AMD Announces Threadripper 2, Chiplets Aid Core Scaling

August 7, 2018May 25, 2021 David Schor 12LP, 12nm, AMD, HEDT, Ryzen Threadripper, x86, Zen

AMD announces their second-generation Threadripper processors with up to 32 cores based on their 12nm Zen+ microarchitecture.

Foundries Process Technologies VLSI 2018

VLSI 2018: GlobalFoundries 12nm Leading-Performance, 12LP

July 22, 2018May 25, 2021 David Schor 12 nm, 12LP, 14 nm, 14LPP, FinFET, GlobalFoundries, process technology

A look at GlobalFoundries 12nm Leading Performance technology, 12LP, an enhanced 14nm process. The process was recently presented at the 2018 Symposia on VLSI Technology and Circuits.