WikiChip Fuse
A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

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IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.

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GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

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A Look At The Ice Lake Thunderbolt 3 Integration

At look the Ice Lake Thunderbolt 3 integration, Intel’s biggest integration since the graphics on Sandy Bridge.

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Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects

Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.

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Nvidia Inference Research Chip Scales to Dozens of Chiplets

Nvidia recently presented a research chip comprising dozens of chiplets that enables them to scale from milliwatts to hundreds of watts in order to cater to different markets such as edge, mobile, automotive, and data center.

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TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

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Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

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