Interconnects

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020 David Schor 3 Comments 2.5D packaging, 3D packaging, Co-EMIB, EMIB, Foveros, Intel

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Interconnects Packaging Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020 David Schor 0 Comments co-packaged optics (CPO), co-packaging, Ranovus, Ranovus Odin, silicon photonics

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020 David Schor 0 Comments 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020 David Schor 2 Comments 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

Architectures Hot Interconnects 26 Interconnects Supercomputers

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020 David Schor 0 Comments 16 nm, Cray, Cray Shasta, Cray Slingshot, Ethernet switch, Hot Interconnects, Hot Interconnects 26

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

Architectures Circuit Design Hot Chips 31 Interconnects Packaging

Ayar Labs Realizes Co-Packaged Silicon Photonics

January 19, 2020 David Schor 0 Comments 45 nm, 45RFSOI, Ayar Labs, chiplet, GlobalFoundries, GlobalFoundries Technology Conference (GTC), Hot Chips, Hot Chips 31, Intel, multi-chip package, Photonics, silicon photonics, Stratix 10, TeraPHY

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

Hot Interconnects Hot Interconnects 26 Interconnects

OCP Bunch of Wires: A New Open Chiplets Interface For Organic Substrates

January 5, 2020 David Schor 0 Comments Bunch of Wires (BoW), chiplet, Hot Interconnects, Hot Interconnects 26, multi-chip package, OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

A look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.

Interconnects Packaging

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020 David Schor 0 Comments 2.5D packaging, Advanced Interface Bus (AIB), chiplet, EMIB, interposer, OCP Accelerator Module (OAM), OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019 David Schor 0 Comments 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

Architectures Hot Chips 31 Interconnects Neural Processors Packaging

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

November 16, 2019 David Schor 0 Comments 16nm, AI, Cerebras, Hot Chips, Hot Chips 31, neural processors, training, Wafer-Scale Engine (WSE)

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

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