Interconnects

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor 12 nm, 12LP, 3D packaging, ARM, CMN-600, die stacking, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, IEDM, IEDM 2020, subscriber only (general), Trishul (Arm test chip)

With hybrid bonding inching towards production, here’s a look at Trishul, Arm’s first exploratory test chip – in collaboration with GlobalFoundries – that demonstrates the feasibility of high-density 3D stacking using Arm’s CoreLink CMN-600 extended to 3D.

Architectures Desktop Processors Interconnects Packaging

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor 3D packaging, 3D V-Cache, 7 nm, AMD, Direct Bond Interconnect (DBI), hybrid bonding, Ryzen, SRAM, System on Integrated Chips (SoIC)

AMD recently unveiled 3D V-Cache, their first 3D-stacked technology-based product. Leapfrogging contemporary 3D bonding technologies, AMD jumped directly into advanced packaging with direct bonding and an order of magnitude higher wire density.

Architectures Interconnects Network-on-Chip

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, cache coherency, CI-700, CMN-700, CoreLink, interconnects, Memory Tagging Extension (MTE), mesh interconnect, NI-700

Arm is introducing a new cache-coherent and SoC-level interconnects, the CoreLink CI-700 & NI-700.

Architectures Interconnects Mobile Processors

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor ARM, ARMv9, DSU-110, Memory Tagging Extension (MTE)

Arm introduces its new DynamIQ Share Unit 110 for new Armv9 CPUs

Architectures Interconnects

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor ARM, CMN-600, CMN-700, DDR5, mesh interconnect, neoverse, Neoverse N, Neoverse V, PCIe 5.0

Arm’s CMN-700 is the company’s latest high-performance cache-coherent mesh interconnect for the server market, enabling SoC designs with twice as many cores, as much as half a GiB of cache, dozens of memory controllers, and support dozens of cache-coherent accelerators, chiplets, and processors.

Interconnects Packaging Process Technologies

Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

May 17, 2020May 23, 2021 David Schor 2.5D packaging, 3D packaging, Co-EMIB, EMIB, Foveros, Intel

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

Interconnects Packaging Silicon Photonics

Ranovus Odin: Co-Packaging Next-Gen DC Switches and Accelerators With Silicon Photonics

April 11, 2020May 25, 2021 David Schor co-packaged optics (CPO), co-packaging, Ranovus, Ranovus Odin, silicon photonics

Ranovus launches its Odin platform, a multi-wavelength Quantum Dot Laser (QDL) based silicon photonic engine which includes 800Gbps to 3.2Tbps single-chip engines as well as co-packaged optics scaling up to 51.2Tbps for next-generation data center switches and other HPC compute chips that require high bandwidth capacity.

Interconnects Packaging Process Technologies

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

March 3, 2020May 25, 2021 David Schor 2.5D packaging, 5 nm, 7 nm, CoWoS, interposer

TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020May 25, 2021 David Schor 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.