Interconnects

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

David SchorArchitectures, Interconnects, Packaging, Process TechnologiesSeptember 21, 2019 Tagged 12LP, 12nm, 3D packaging, ARM, design-for-test, GlobalFoundries, hybrid bonding

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

A Look At The Ice Lake Thunderbolt 3 Integration

David SchorArchitectures, InterconnectsAugust 11, 2019 Tagged 10nm, Ice Lake, Thunderbolt, Thunderbolt 3, USB 3.1, USB 4, x86

At look the Ice Lake Thunderbolt 3 integration, Intel’s biggest integration since the graphics on Sandy Bridge.

Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects

David SchorInterconnects, PackagingJuly 9, 2019 Tagged 3D packaging, Co-EMIB, EMIB, Foveros, SemiCon, SemiConWest

Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.

Nvidia Inference Research Chip Scales to Dozens of Chiplets

David SchorArchitectures, Interconnects, Neural Processors, VLSI 2019June 30, 2019 Tagged 16nm, chiplet, ground-referenced signaling, multi-chip package, neural processors, Nvidia, RISC-V

Nvidia recently presented a research chip comprising dozens of chiplets that enables them to scale from milliwatts to hundreds of watts in order to cater to different markets such as edge, mobile, automotive, and data center.

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TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

David SchorInterconnects, Packaging, Server Processors, VLSI 2019June 22, 2019 Tagged 7nm, ARM, ARMv8, chiplet, Cortex-A72, CoWoS, LIPINCON, TSMC, VLSI 2019, VLSI Symposium

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

David SchorFoundries, Interconnects, Packaging, Process TechnologiesMay 11, 2019 Tagged 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

David SchorArchitectures, Floorplanning, Hot Chips 30, Interconnects, Server ProcessorsOctober 7, 2018 Tagged 14HP, 14nm, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

Nantero’s NRAM, A Universal Memory Candidate?

David SchorHot Chips 30, Interconnects, Process TechnologiesSeptember 22, 2018 Tagged 28nm, carbon nanotube, carbon nanotubes, CNTs, Nantero, non-volatile memory, NRAM, process technology, storage-class memory

Presented at Hot Chips 30, a look at Nantero’s NRAM, a high-performance carbon nanotube-based memory billed as a DRAM successor.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

David SchorERI Summit 2018, InterconnectsJuly 24, 2018 Tagged Advanced Interface Bus, AIB, DARPA, EMIB, Intel, interconnects, Packaging

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.