Interconnects

Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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POWER9 Scales Up To 1.2 TB/s of I/O, Targets NVLink 3, OpenCAPI Memory for 2019

David SchorArchitectures, Floorplanning, Hot Chips 30, Interconnects, Server ProcessorsOctober 7, 2018 Tagged 14HP, 14nm, A-Bus, Centaur, Hot Chips, Hot Chips 30, IBM, NVLink, OpenCAPI, POWER, POWER9, PowerAXON, X-Bus

A look at the IBM POWER9 scale-up design recently disclosed at Hot Chips 30 and their plans for a 3rd POWER9 derivative for 2019.

Nantero’s NRAM, A Universal Memory Candidate?

David SchorHot Chips 30, Interconnects, Process TechnologiesSeptember 22, 2018 Tagged 28nm, carbon nanotube, carbon nanotubes, CNTs, Nantero, non-volatile memory, NRAM, process technology, storage-class memory

Presented at Hot Chips 30, a look at Nantero’s NRAM, a high-performance carbon nanotube-based memory billed as a DRAM successor.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

David SchorInterconnectsJuly 24, 2018 Tagged Advanced Interface Bus, AIB, DARPA, EMIB, Intel, interconnects, Packaging

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.