Interconnects

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020May 25, 2021 David Schor 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

Architectures Hot Interconnects 26 Interconnects Supercomputers

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020May 25, 2021 David Schor 16 nm, Cray, Cray Shasta, Cray Slingshot, Ethernet switch, Hot Interconnects, Hot Interconnects 26

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

Architectures Circuit Design Hot Chips 31 Interconnects Packaging

Ayar Labs Realizes Co-Packaged Silicon Photonics

January 19, 2020May 25, 2021 David Schor 45 nm, 45RFSOI, Ayar Labs, chiplet, GlobalFoundries, GlobalFoundries Technology Conference (GTC), Hot Chips, Hot Chips 31, Intel, multi-chip package, Photonics, silicon photonics, Stratix 10, TeraPHY

Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.

Hot Interconnects Hot Interconnects 26 Interconnects

OCP Bunch of Wires: A New Open Chiplets Interface For Organic Substrates

January 5, 2020May 25, 2021 David Schor Bunch of Wires (BoW), chiplet, Hot Interconnects, Hot Interconnects 26, multi-chip package, OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

A look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.

Interconnects Packaging

OCP Makes a Push for an Open Chiplet Marketplace

January 4, 2020May 25, 2021 David Schor 2.5D packaging, Advanced Interface Bus (AIB), chiplet, EMIB, interposer, OCP Accelerator Module (OAM), OCP Open Domain-Specific Architecture (ODSA), Open Compute Project (OCP)

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019May 25, 2021 David Schor 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

Architectures Hot Chips 31 Interconnects Neural Processors Packaging

A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

November 16, 2019May 25, 2021 David Schor 16nm, AI, Cerebras, Hot Chips, Hot Chips 31, neural processors, training, Wafer-Scale Engine (WSE)

A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.

Architectures Hot Chips 31 Interconnects Server Processors

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

November 3, 2019May 25, 2021 David Schor Centaur (buffer chip), Hot Chips 31, IBM, NVLink, Open Memory Interface (OMI), open source, OpenCAPI, Power ISA, POWER9

IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.

Architectures Interconnects Packaging Process Technologies

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

September 21, 2019June 11, 2021 David Schor 12LP, 12nm, 3D packaging, ARM, CMN-600, design-for-test, Direct Bond Interconnect (DBI), GlobalFoundries, hybrid bonding, Trishul (Arm test chip)

GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.

Architectures Interconnects

A Look At The Ice Lake Thunderbolt 3 Integration

August 11, 2019May 25, 2021 David Schor 10nm, Ice Lake, Thunderbolt, Thunderbolt 3, USB 3.1, USB 4, x86

At look the Ice Lake Thunderbolt 3 integration, Intel’s biggest integration since the graphics on Sandy Bridge.