Your Chips and Semi News
TSMC announces an enhancement to its CoWoS packaging technology with support for up to 2x the reticle size. The new technology is ready for next-generation 5-nanometer HPC applications.
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The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.
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A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.
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Integrated photonics has long been considered a holy grail for communication. Ayar Labs TeraPHY chiplet represents a major step forward through the co-packaging of the optical interface along with an SoC.
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A look at a Bunch of Wires, a new open standard chiplets interconnect being proposed by the OCP ODSA group intended for standard organic multi-chip packages as a cheaper alternative to silicon interposers and bridges.
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Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.
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TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.
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A look at Cerebras Wafer-Scale Engine (WSE), a chip the size of a wafer, packing over 400K tiny AI cores using 1.2 trillion transistors on a half square foot of silicon.
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IBM adds a third variant of POWER9, the POWER9 Advanced I/O (AIO) processor which incorporates the Open Memory Interface (OMI), a new open memory-agnostic interface.
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GlobalFoundries and Arm demonstrate a 3D mesh interconnect design using highly-dense hybrid bonding 3D stacking technology intended for HPC applications.
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