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Wednesday, May 18, 2022
Latest:
  • Reincarnating The 6502 Using Flexible TFT Tech For IoT
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC
  • Samsung-Esperanto Concept AI-SSD Prototype
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization
  • Intel Launches 12th Gen Core Desktop Alder Lake Processors
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Cray Slingshot

Architectures Hot Interconnects 26 Interconnects Supercomputers 

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020May 25, 2021 David Schor 16 nm, Cray, Cray Shasta, Cray Slingshot, Ethernet switch, Hot Interconnects, Hot Interconnects 26

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

Read more

Top Six Articles

  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
  • TSMC 2021 Foundry Update: Foundry Roadmap
  • Intel Announces 20Å Node: RibbonFET Devices, PowerVia, 2024 Ramp
  • AMD 3D Stacks SRAM Bumplessly

Recent

  • Reincarnating The 6502 Using Flexible TFT Tech For IoT

    Reincarnating The 6502 Using Flexible TFT Tech For IoT

    May 8, 2022May 8, 2022 David Schor
  • Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    Intel Unveils BonanzaMine, A Bitcoin Accelerator ASIC

    February 20, 2022February 21, 2022 David Schor
  • Samsung-Esperanto Concept AI-SSD Prototype

    Samsung-Esperanto Concept AI-SSD Prototype

    November 21, 2021November 21, 2021 David Schor
  • EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

    November 20, 2021November 20, 2021 David Schor
  • Intel Launches 12th Gen Core Desktop Alder Lake Processors

    Intel Launches 12th Gen Core Desktop Alder Lake Processors

    October 27, 2021November 3, 2021 David Schor
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

    TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

    October 26, 2021October 26, 2021 David Schor

Random Picks

X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

February 5, 2018May 25, 2021 David Schor
Fujitsu Semi Sells 300mm Mie Fabs

Fujitsu Semi Sells 300mm Mie Fabs

June 29, 2018May 25, 2021 David Schor
The Fuse!

The Fuse!

October 30, 2017May 25, 2021 David Schor
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020May 25, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random Tags

2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 12nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET Foveros GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

Mythic Rolls Out M1000-Series Analog AI Accelerators; Raises $70M Along The Way

August 22, 2021August 22, 2021 David Schor
Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

November 7, 2019May 25, 2021 David Schor
Intel axes Knights Hill, plans a new microarchitecture for exascale

Intel axes Knights Hill, plans a new microarchitecture for exascale

November 14, 2017May 25, 2021 David Schor
Ayar Labs Realizes Co-Packaged Silicon Photonics

Ayar Labs Realizes Co-Packaged Silicon Photonics

January 19, 2020May 25, 2021 David Schor
AMD 3D Stacks SRAM Bumplessly

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor
WikiChip Fuse Moves to a Decaying Paywall Model

WikiChip Fuse Moves to a Decaying Paywall Model

May 13, 2021May 23, 2021 David Schor
TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

June 16, 2019May 25, 2021 David Schor

ARM WorldView All

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor
A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip
IEDM 2020 Interconnects Packaging Subscriber Only Content 

A Look At Trishul: Arm’s First High-Density 3D Logic Stacked Test-Chip

June 11, 2021June 11, 2021 David Schor
Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700
Architectures Interconnects Network-on-Chip 

Arm Launches New Coherent And SoC Interconnects: CI-700 & NI-700

May 25, 2021May 25, 2021 David Schor
Arm Launches The DSU-110 For New Armv9 CPU Clusters
Architectures Interconnects Mobile Processors 

Arm Launches The DSU-110 For New Armv9 CPU Clusters

May 25, 2021May 25, 2021 David Schor

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