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  • Intel Launches 3rd Gen Ice Lake Xeon Scalable
  • Arm Highlights Near-Term Roadmap
  • Arm Launches ARMv9
  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
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Cray Slingshot

Architectures Hot Interconnects 26 Interconnects Supercomputers 

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020 David Schor 0 Comments 16 nm, Cray, Cray Shasta, Cray Slingshot, Ethernet switch, Hot Interconnects, Hot Interconnects 26

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

Read more

Top Six Articles

  • A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip
  • TSMC Details 5 nm
  • Intel Launches 3rd Gen Ice Lake Xeon Scalable
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
  • Arm Unveils the Cortex-A78: When Less Is More
  • IEDM 2017 + ISSCC 2018: Intel’s 10nm, switching to cobalt interconnects

Recent

  • Intel Launches 3rd Gen Ice Lake Xeon Scalable

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1
  • Arm Highlights Near-Term Roadmap

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
  • Arm Launches ARMv9

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
  • Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
  • The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
  • Arm’s New Cortex-M55 Breathes Helium

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
  • Comment
  • Recent
  • JayN says:

    Interesting addition of avx512 IFMA. A 2018 artic...

  • Briny says:

    Given how often secure architectures have been bro...

  • Piotr says:

    Will SVE2 be mandatory in ARMv9 or not?...

  • Asd says:

    A popup asked me to comment, so here's a comment!...

  • Not Ludwig says:

    Intel has already canceled this chip so it doesn't...

  • Intel Launches 3rd Gen Ice Lake Xeon Scalable

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1
    Arm Highlights Near-Term Roadmap

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
    Arm Launches ARMv9

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10

    Random Picks

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    x86 WorldView All

    Intel Launches 3rd Gen Ice Lake Xeon Scalable
    Architectures Server Processors 

    Intel Launches 3rd Gen Ice Lake Xeon Scalable

    April 6, 2021April 6, 2021 David Schor 1

    Intel launches its 3rd Generation Xeon Scalable, formerly Ice Lake. Fabricated on the company’s 10nm process, those server chips go up to 40 Sunny Cove cores and offer a 20% IPC improvement over the prior generation.

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids
    Architectures 

    The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations; To Debut with Sapphire Rapids

    June 29, 2020September 19, 2020 David Schor 10
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    Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

    December 12, 2019 David Schor 0
    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512
    Architectures Embedded Processors Neural Processors Server Processors 

    Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

    December 9, 2019 David Schor 3
    SC19: Aurora Supercomputer To Feature Intel First Exascale Xe GPGPU, 7nm Ponte Vecchio
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    Random

    TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

    TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

    April 17, 2020 David Schor 6
    Intel launches Gemini Lake

    Intel launches Gemini Lake

    December 11, 2017 David Schor 0
    TSMC Details 5 nm

    TSMC Details 5 nm

    March 21, 2020 David Schor 4
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    January 19, 2018 David Schor 0
    Intel silently launches Knights Mill

    Intel silently launches Knights Mill

    December 18, 2017 David Schor 0
    Samsung 5 nm and 4 nm Update

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    October 19, 2019 David Schor 3
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    ARM WorldView All

    Arm Highlights Near-Term Roadmap
    Roadmaps 

    Arm Highlights Near-Term Roadmap

    April 4, 2021April 5, 2021 David Schor 0
    Arm Launches ARMv9
    Architectures Roadmaps 

    Arm Launches ARMv9

    March 30, 2021March 30, 2021 David Schor 3
    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support
    Roadmaps Server Processors 

    Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support

    September 22, 2020September 30, 2020 David Schor 3
    Arm’s New Cortex-M55 Breathes Helium
    Architectures Embedded Processors 

    Arm’s New Cortex-M55 Breathes Helium

    June 20, 2020 David Schor 0
    Arm Unveils the Cortex-A78: When Less Is More
    Architectures Mobile Processors 

    Arm Unveils the Cortex-A78: When Less Is More

    May 26, 2020 David Schor 0
    Arm Cortex-X1: The First From The Cortex-X Custom Program
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    Arm Cortex-X1: The First From The Cortex-X Custom Program

    May 26, 2020 David Schor 0

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