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Sunday, March 26, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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16 nm

Architectures FPGAs Subscriber Only Content 

Intel’s Diamond Mesa Bridges The Gap Between ASIC and FPGA

June 13, 2021June 13, 2021 David Schor 16 nm, Diamond Mesa, eASIC Nextreme, Intel, Intel eASIC, Structured ASIC, subscriber only (general)

With Intel’s acquisition of eASIC in 2018, the company’s latest product – codenamed Diamond Mesa – attempts to bridge the gap between full ASIC and FPGAs.

Read more
Architectures Hot Interconnects 26 Interconnects Supercomputers 

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020May 25, 2021 David Schor 16 nm, Cray, Cray Shasta, Cray Slingshot, Ethernet switch, Hot Interconnects, Hot Interconnects 26

A dive into the Rosetta ASIC switch, the engine behind Cray’s new Slingshot interconnect powering the upcoming Shasta exascale supercomputers.

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Top Six Articles

  • A Look At Intel 4 Process Technology
  • IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips
  • Arm Introduces The Cortex-A715
  • N3E Replaces N3; Comes In Many Flavors

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

SEMICON West 2019: ASML EUV Update

SEMICON West 2019: ASML EUV Update

July 21, 2019May 25, 2021 David Schor
Intel Announces Keem Bay: 3rd Generation Movidius VPU

Intel Announces Keem Bay: 3rd Generation Movidius VPU

November 12, 2019May 25, 2021 David Schor
UMC Rolls Out 22-Nanometer

UMC Rolls Out 22-Nanometer

December 13, 2019May 25, 2021 David Schor
Intel Silently Launches Cannon Lake

Intel Silently Launches Cannon Lake

May 15, 2018May 25, 2021 David Schor
Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance

Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance

May 26, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor
IEDM 2017: AMD’s grand vision for the future of HPC

IEDM 2017: AMD’s grand vision for the future of HPC

December 5, 2017May 25, 2021 David Schor
Intel Silently Launches Cannon Lake

Intel Silently Launches Cannon Lake

May 15, 2018May 25, 2021 David Schor
Centaur New x86 Server Processor Packs an AI Punch

Centaur New x86 Server Processor Packs an AI Punch

January 24, 2020May 25, 2021 David Schor
IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

November 3, 2019May 25, 2021 David Schor
PEZY dominates the new Green500 list

PEZY dominates the new Green500 list

November 13, 2017May 25, 2021 David Schor
Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

May 13, 2021May 23, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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