Intel discloses Tremont, a Goldmont Plus successor
Intel has released the latest revision of their architecture ISA programming reference and with it are some new interesting details.
The latest microarchitecture disclosed is “Tremont” which looks to succeed Goldmont Plus. In fact, since we now have a name, a bit of searching revealed Intel has already submitted an initial patch back on March 1st confirming this.
From the kernel patch, it appears that the platform name will be called “Jacobsville” (Family 6, Model 134). Additionally, there is a comment that references 10nm so it looks like this might be the first Atom core to be fabricated on Intel’s 10nm process.
From the programming reference manual, the new microarchitecture is listed as having the following new instructions:
- CLWB – Force cache line write-back without flush
- CLDEMOTE – Cache line demote instruction
- ENCLV – SGX oversubscription instructions
- GFNI – Galois Field New Instructions (GFNI)
- Direct store instructions – direct store using write combining (WC) for doublewords (MOVDIRI) and 64B (MOVDIR64B)
- User wait and address monitor/wait instructions – (TPAUSE, UMONITOR, UMWAIT)
- Split Lock Detection – detection and cause an exception for split locks
The CLDEMOTE instruction “demotes” a cache line containing a specific address from the nearest cache to a more distant level (e.g., from an L1 to an L2/L3, though hardware decides) without writing back to memory. This is an optimization instruction intended to accelerate subsequent accesses to the line by other cores.
The Galois Field New Instructions (GFNI) extension comes in a couple of flavors – GFNI, AVX GFNI, and AVX-512 GFNI. Ice Lake will feature all three variants while Tremont will have the SSE version only. This is expected given the Atom line doesn’t have any of the AVX extensions (1/2/512) supported.
By the way, late last year we mentioned that Intel is introducing a new Total Memory Encryption (TME) extension for full memory encryption. It looks like this extension will be introduced in the Ice Lake (server) microarchitecture.
Derived WikiChip Articles: Tremont, Ice Lake (Server), Intel.