x86 – WikiChip Fuse

Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

David SchorArchitectures, Desktop Processors, Roadmaps, Server ProcessorsDecember 23, 2018 Tagged 10nm, 7nm, AVX-512, Foveros, Golden Cove, Gracemont, Ice Lake, Palm Cove, Sunny Cove, Tremont, Willow Cove, x86

Last week Intel disclosed initial details of their next-generation core microarchitecture, Sunny Cove, which will make it into future Ice Lake client and server chips among other products.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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AMD Discloses Initial Zen 2 Details

David SchorArchitectures, Server ProcessorsNovember 18, 2018 Tagged 14nm, 7nm, AMD, Rome, x86, Zen, Zen 2, Zen 4

Following AMD’s recent Zen 2 and Rome disclosure, here’s a look at what has changed and what second-generation EPYC brings to the table.

Intel Cascade Lake Brings Hardware Mitigations, AI Acceleration, SCM Support

David SchorArchitectures, Hot Chips 30, Server ProcessorsNovember 11, 2018 Tagged 14nm, AVX-512, AVX512VNNI, Cascade Lake, Cascade Lake AP, Cascade Lake SP, CSL, CSX, Intel, persistent memory, SCM, Skylake, storage-class memory, x86

A look at Cascade Lake, Intel’s microarchitecture for next-generation Xeon microprocessors featuring process enhancements, persistent memory support, and AI acceleration.

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