WikiChip Fuse
Zhaoxin Unveiled Next-Generation x86 SoC Plans: 32-Core Servers, Sub-7nm Client Designs

Zhaoxin unveiled plans for two new x86 SoC designs: a high-performance 16-nanometer server chip with up to 32 cores and a separate 7 nm mobile and desktop chip.

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Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

Intel launches a new Stratix 10 family bringing new support for PCIe Gen 4.0, new cache-coherency support, and Optane DC DIMM support.

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Intel Introduces 10nm Agilex FPGAs; Customized Connectivity with HBM, DDR5, PCIe Gen 5, and  112G Transceivers

Intel has introduced their next-generation flagship data center FPGAs based on their 10-nanometer process. Utilizing a chiplet-based architecture, the company hopes to better customize the product for customer’s demand while iterating faster on PHYs and other connectivity protocols.

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ORNL’s 200-petaFLOPS Summit Supercomputer Has Arrived, To Become World’s Fastest

A look at the 200-petaFLOPS Summit supercomputer which was officially unveiled last Friday by Oak Ridge National Laboratory (ORNL).

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