WikiChip Fuse
Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

Read more
Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

Intel launches a new Stratix 10 family bringing new support for PCIe Gen 4.0, new cache-coherency support, and Optane DC DIMM support.

Read more
DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

Read more
Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects

Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.

Read more
Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Read more
Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

Read more
Hot Chips 30: Intel Kaby Lake G

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

Read more
Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

Read more
Intel launches 8th Gen Core with Radeon RX Vega Graphics

At CES 2018 Intel announced the first series of the much anticipated Core i5 and i7 chips with Radeon graphics. Those parts incorporate a Kaby Lake microprocessor, a Vega M GPU, and 4 GiB of HBM2 cache.

Read more
Intel to leverage EMIBs to create mobile processors with discrete AMD graphics

Intel has announced they will be introducing an 8th generation processor featuring a discrete AMD Radeon GPU along with HBM2. Using Intel’s new EMIB packaging interconnect technology, the single-chip solution provides higher performance while delivering a smaller form factor than comparable solutions.

Read more