WikiChip Fuse
Left, Right, Above, and Under: Intel 3D Packaging Tech Gains Omnidirectionality

A look at ODI, a new family of packaging interconnect technologies that bridges the gap between Intel’s EMIB (2.5D) and Foveros (3D) by providing the flexibility of an EMIB in 3D with additional benefits of thermal & power.

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OCP Makes a Push for an Open Chiplet Marketplace

Jumping ahead of emerging semiconductor trends, the OCP new Open Domain-Specific Architecture subgroup makes a push for an open and standardized chiplet interface and marketplace.

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Intel Launches Stratix 10 GX 10M; 10M LEs, Two Massive Interconnected Dies

Intel launches the industry’s highest-capacity FPGA; 10-million LEs comprising two large FPGA dies interconnected using the company’s 2.5D EMIB packaging technology.

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Intel Stratix 10 DX Adds PCIe Gen 4.0, Cache Coherency: UPI As Stopgap

Intel launches a new Stratix 10 family bringing new support for PCIe Gen 4.0, new cache-coherency support, and Optane DC DIMM support.

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DARPA ERI: How Ayar Labs Collaboration With GF Produces A Photonics Chiplet That Can Supercharge Intel FPGAs

From a DARPA vision and a $15 million seed to a commercialized CMOS silicon photonics product: how Ayar Labs collaboration with GF produces a photonics chiplet that can supercharge Intel FPGAs.

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Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects

Intel is expanding its packaging portfolio with more advanced 2.5D and 3D technologies including multiple 3D stacks and omnidirectional interconnects.

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Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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Hot Chips 30: Intel Kaby Lake G

A look at Intel’s current generation of Thin & Light processors with high-performance graphics, formerly known as Kaby Lake G, from Hot Chips 30.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

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