A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium

Early last month, Intel quietly launched a somewhat odd 10 nm part. This processor was shipped in limited quantities in a Lenovo IdeaPads 330. The chip is based on the Cannon Lake microarchitecture but comes with a disabled GPU. Lenovo fixed this by dropping an AMD Radeon RX 540 in there. Lucky for us, TechInsights has managed to get their hands on that laptop and have done an analysis of the chip.

Package, Die Size

As far back as just a few years ago when Broadwell was introduced, Intel was very transparent about their process technology, architecture, and chips. Packaging, die size, and other technical information was abundant.


Haswell-Broadwell Dual-core comparison (Intel)

Unfortunately, over the last few years, it’s been missing. Intel has been increasingly light on technical details. Trivial information such as die size and transistor count is now confidential. Fortunately, technology intelligence companies such as TechInsights have been instrumental in demystifying some of the details.

Techinsights has confirmed the chip in the Lenovo IdeaPad 330 is the 10nm Cannon Lake Core i3-8121U, s-spec ‘SRCVC’. They have not mentioned a die size but since Intel revealed that the BGA packaging size is 45mm x 24mm, we can do the math ourselves. We have calculated the die to be 8.2 mm by 8.6 mm for a total area of ~70.52 mm². In fact, Ian Cutress over at AnandTech managed to calculate that exact die size from the photo that was shot at Intel’s Tech Day China last year.

WikiChip’s die size measurement using TechInsights Photo (Photo Credit: TechInsights, published with permission)

At ~70.52 mm², the Cannon Lake die appears to be the smallest dual-core die Intel has ever made, at least as far as the “big cores” are concerned.

Standard Cells

Earlier this year, WikiChip was able to confirm with Intel the exact layout of their 10nm cells during ISSCC 2018. Given the ongoing confusion of the track design, we have decided to take this opportunity to fully explain the cell design.


As far as cell size is concerned, there are no surprises. TechInsights silicon measurements matches Intel’s own IEDM paper. The metal pitch has shrunk from 52nm to 36nm and the gate pitch shrunk from 70nm to 54nm. They use contact-on-active gate (COAG) and have shrunk the cell height to 272 nanometers.

Since Intel has been using FinFETs for their 22, 14 and 10-nanometer processes, their standard cells are all fin-quantize. A standard cell is 272nm high and comprises eight diffusion lines. This is a reduction of 0.68x from the 399nm which consisted of 10 lines (actually 9.5 lines high, but based on 10 lines) which was a reduction from 14 lines at the 22nm node.

Intel’s Cell Height (WikiChip)

With eight diffusion lines, it means Intel can only pack 5 active fins. In other words, they are using 3 N fins and 2 P fins for their standard library.

Intel’s 10nm Standard Cell Active Fins (WikiChip)

If we were to design something like a NAND2 gate, then we would have two active gates and a single dummy gate at each of the cell boundaries. In other words, the width of the cell would be three gate pitches wide. TechInsights has measured a 54nm minimum gate pitch (identical to Intel’s IEDM paper), therefore the NAND2 cell width is 162 nanometers wide.

NAND2 Cell with only Fins and Gates shown. (WikiChip)

Intel’s first metal layer (M0) has a pitch of 40 nm. Techinsights has confirmed Intel is using contact-on-active gate (COAG). While the contact over the source-drain can be in the active region, the gate contact is traditionally dropped off the active region and over the isolation region. This is done to prevent shorting the gate. For their 10nm, Intel introduced the COAG process in order to allow the gate contact to be dropped right on top of the active gate, thereby further compaction the cell height.


Intel’s COAG Process (WikiChip)

Continuing to build the cell from before, the M0 layer with a 40nm pitch now spans the cell with the COAG dropping down directly to the gate electrode below it.

M0 and COAG placement (WikiChip)

The tightest pitches reported to date come from their Metal 1 layer with 36-nanometer pitches. Intel’s M1 is actually unusually dense, allowing for a great number of possible combinations of valid pin points to the M2 above. This is likely a key enabler for the efficient routing of their dense 10nm cells.

M1 Wires (WikiChip)

The Metal 2 track height measured by TechInsights is 6.2-Track high which also matches what Intel reported. With a cell height of 272nm and an M2 pitch of 44nm, there are 7 tracks which are shown below.

Metal 2 layer on top of prior layer (WikiChip)


As far as density is concerned, the Core i3-8121U uses a process with a density, based on Intel’s metric, of 100.76 MTr/mm². This is a result of a transistor density of 90.78 MTr/mm² for packed NAND2 gates and 115.74 MTr/mm² for packed SSF cells.

Intel’s FinFET Processes (WikiChip)

Cobalt, Ruthenium

The minimum design rules for Intel’s 10nm are shown below. For the nitty-gritty stuff, check out our detailed article from IEDM. For the three lowest layers (poly, metal 0, and metal 1), Intel introduced Cobalt and Tungsten. What’s interesting though is that TechInsights also found Ruthenium along with Cobalt in the metallization stack. Intel has never mentioned using Ruthenium for their process at any of the conferences we have attended (including VLSI, ISSCC, and IEDM). However, this isn’t too surprising because in recent years Cobalt, Ruthenium, and Manganese were discussed by both Intel and Applied Materials as possible future metallization schemes. It’s worth noting that Samsung, IBM, and GlobalFoundries have also discussed Cobalt and Ruthenium for sub-7nm nodes in past conferences.

Design Rules
Layer Pitch (nm) Metal Patterning
Fin 34 SAQP
Poly 54 with Co SADP
Metal 0 40 Co SAQP
Metal 1 36 Co SAQP
Metal 2 44 Cu SADP
Metal 3 44 Cu SADP
Metal 4 44 Cu SADP
Metal 5 52 Cu SADP
Metal 6 84 Cu Single
Metal 7, 8 112 Cu Single
Metal 9, 10 160 Cu Single
Thick Metal 0 1,080 Cu Single
Thick Metal 1 11,000 Cu Single
WikiChip’s Transistor Diagram (simplified)

As a refresher, we want to point out that both Cobalt and Ruthenium are what’s called barrier-less conductors. They do not need barrier layers like Cu does that have stopped scaling (largely the effect of the industry reaching nanometer-thickness barriers, impacting integrity). Cobalt has shown superior EM and TDDB over copper at high-current low-cross-sectional wires which is one of the primary reasons Intel switched to Cobalt. What’s more interesting is, at last year’s VLSI Symposium, IBM/Globalfoundries reported that the thinnest possible Cu barriers can be achieved by using Cu with TaN/Ru barriers or tCoSFB (Through-Cobalt Self Forming Barrier). By the way, they also claim that Cu with tCoSFB has lower line R than even Co and Ru, meaning there is no cross-over point where Co would be better than Cu. But that seems to go against what Intel is doing with 10nm. It’s unclear who is right. So there is clearly a fork in the road as far as interconnects go.

We do not know exactly where Ru was found (the info is reserved for TechInsights subscribers) but given everything discussed, we suspect Intel is using Ru/Cu wires for their Metal 2, 3, and 4 layers. This is likely done for the exact reason GlobalFoundries reported – create the thinnest possible barrier. It will definitely be interesting to see what the rest of the industry converges on.

Line Resistance for Ru, Co, TaN/Ru/Cu, and tCoSFB. X axis is metal area (nm²) (VLSI 2017, GlobalFoundries)

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2 years ago

Author’s original research in the article raises questions.

E.g. the author says “Earlier this year, WikiChip was able to confirm the exact layout of Intel’s 10nm cells”.
– How?
– By what means?
– Was Intel at all involved in this unexplained confirmation?

We also know GF 7nm has 2×2-fin 6T cells and 2-fin well separation, Intel’s own slides also show 2×2-fin cells, so in case the author is an expert and takes his work seriously, how did he conclude Intel in fact uses 1-fin well separation in their 10nm process?

And in case there was no research whatsoever behind that 3+2 fin design shown, what’s the value of the article at all? And this is not the only question, e.g. how did the author conclude Intel uses hvh and not vhv or mixed routing in their 10nm lib?

Routing scheme is actually one of interesting questions about Intel’s 10nm lib given their choice of fin, contacted poly and metal pitches, but again, the author stops short of showing complete layout with precisely drawn dimensions, which would be interesting to take a look at even for the simple NAND cell that he chose for illustrations.

As for cell height, I suspect it’s not 6.2T, but 6T, as I think Intel simply misquoted their metal pitches by 1nm — you can check my post on RWT for details: https://www.realworldtech.com/forum/?threadid=177542&curpostid=177584

Besides, the picture with M2 metals is drawn simply incorrectly (and explanatory text is incorrect too), 7 tracks don’t fit within the cell height.

It would be nice if the author provides proper comments.

Reply to  David Schor
2 years ago

David, thank for the comments.

I recommend you don’t read too much into Intel’s press material diagrams.

No, it’s not just marketing slides. First, your own article https://fuse.wikichip.org/news/525/iedm-2017-isscc-2018-intels-10nm-switching-to-cobalt-interconnects/6/ shows 2×2-fin cell as well, and if you check Intel’s IEDM paper, they also show 2×2-fin cell design, which is why I’d like some clarification here. Who provided that controversial information and was it done during a presentation, or was it off-stage, off-record comment? Can you share any other details of that clarification you had? And why your previous article shows 2×2-fin layout after all?

There are no mistakes. They use 7 metal 2 tracks for a 6.2T cell height.

David, please understand that 7 metal tracks simply don’t fit in the cell height as shown in your drawing, because 6 x 44nm = 264nm, which leaves only 8nm for the 7th track, which is but a small fraction of it — that is why your drawing is incorrect, along with the explanatory text next to it.

Reply to  David Schor
2 years ago


I’m sending you correct drawings along with your original pic from the article.

If you go with 44nm M2 pitch (as quoted by Intel and as in your article), then the correct drawing is cell_right.png Cell height is 6.2T, and you have only a small fraction of 7th track (8nm) fitting in the cell.

If, however, you use 45nm pitch (as I suspect Intel simply misquoted their M2 pitch by 1nm), then you have a proper 6T cell with 7 tracks — cell_right2.png

Best regards,

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