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TSMC Details 5 nm

Foundries IEDM 2019 ISSCC 2020 Process Technologies March 21, 2020 0

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

Architectures Floorplanning Interconnects ISSCC 2020 February 21, 2020 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

Foundries January 17, 2020 0

7-nanometer contributes the lion’s share of wafer revenue to TSMC’s fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

TSMC Digs Trenches In Search Of Higher Performance

IEDM 2019 Interconnects Packaging Process Technologies December 14, 2019 0

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

TSMC 5-Nanometer Update

ARM TechCon 2019 Foundries Process Technologies November 1, 2019 0

An update on TSMC’s upcoming 5-nanometer process technology.

TSMC N7+ EUV Process Starts Shipping

Process Technologies October 7, 2019 1

TSMC announces its N7+ process which entered HVM earlier this year is now shipping products to market.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

Packaging Process Technologies SEMICON West 2019 VLSI 2019 July 28, 2019 3

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

Interconnects Packaging Server Processors VLSI 2019 June 22, 2019 0

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

Process Technologies VLSI 2019 June 16, 2019 6

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

TSMC Announces 6-Nanometer Process

Process Technologies April 16, 2019 0

TSMC announces the 6-nanometer process, an enhanced 7 nm EUV node.