TSMC – WikiChip Fuse

TSMC N3, And Challenges Ahead

May 27, 2023May 27, 2023 David Schor 2023 2023 Technology Symposium, 3 nm, IEDM, IEDM 2022, N3, N3B, N3E, TSMC, TSMC Technology Symposium

A Look At TSMC N3 Process

Foundries IEDM 2022

IEDM 2022: Did We Just Witness The Death Of SRAM?

December 14, 2022December 15, 2022 David Schor 3 nm, cache, IEDM, N3, N3B, N3E, SRAM, TSMC

IEDM 2022: Did we just witness the death of SRAM? While foundries continue to show strong logic transistor scaling, SRAM scaling has completely collapsed.

Packaging Subscriber Only Content

TSMC Demos SoIC_H for High-Bandwidth HPC Applications

October 4, 2022October 4, 2022 David Schor 2.5D packaging, 3D packaging, HPC, hybrid bonding, SoIC, SoIC_H, SRAM cube, subscriber only (general), TSMC

[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.

Process Technologies

N3E Replaces N3; Comes In Many Flavors

September 4, 2022September 4, 2022 David Schor 3 nm, FinFlex, N3, N3E, TSMC

TSMC outlines a number of 3-nanometer class node changes and flavors.

Foundries Process Technologies Roadmaps

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor 5 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N4, N4P, N5, TSMC

TSMC introduces a new 5-nanometer derivative – an enhanced performance N4P node.

Architectures Server Processors

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor 5 nm, Alibaba, Apsara Conference 2021, ARM, ARMv9, Panjiu, RISC-V, T-Head, TSMC, Xuantie, Yitian 710

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

Packaging Subscriber Only Content

5th Gen CoWoS-S Extends 3 Reticle Size

August 2, 2021August 2, 2021 David Schor 2.5D packaging, CoWoS, HBM2e, HBM3, interposer, subscriber only (general), TSMC

TSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.

Architectures Manycore Processors

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI

July 10, 2021August 2, 2021 David Schor 7 nm, Esperanto, ET-Maxion, ET-Minion, ET-SoC-1, neural processors, RISC-V, TSMC

A look at Esperanto’s ET-SoC-1, the startup’s first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.