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Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
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TSMC

Foundries IEDM 2022 

IEDM 2022: Did We Just Witness The Death Of SRAM?

December 14, 2022December 15, 2022 David Schor 3 nm, cache, IEDM, N3, N3B, N3E, SRAM, TSMC

IEDM 2022: Did we just witness the death of SRAM? While foundries continue to show strong logic transistor scaling, SRAM scaling has completely collapsed.

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Packaging Subscriber Only Content 

TSMC Demos SoIC_H for High-Bandwidth HPC Applications

October 4, 2022October 4, 2022 David Schor 2.5D packaging, 3D packaging, HPC, hybrid bonding, SoIC, SoIC_H, SRAM cube, subscriber only (general), TSMC

[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.

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Process Technologies 

N3E Replaces N3; Comes In Many Flavors

September 4, 2022September 4, 2022 David Schor 3 nm, FinFlex, N3, N3E, TSMC

TSMC outlines a number of 3-nanometer class node changes and flavors.

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Foundries Process Technologies Roadmaps 

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor 5 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N4, N4P, N5, TSMC

TSMC introduces a new 5-nanometer derivative – an enhanced performance N4P node.

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Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor 5 nm, Alibaba, Apsara Conference 2021, ARM, ARMv9, Panjiu, RISC-V, T-Head, TSMC, Xuantie, Yitian 710

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

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Packaging Subscriber Only Content 

5th Gen CoWoS-S Extends 3 Reticle Size

August 2, 2021August 2, 2021 David Schor 2.5D packaging, CoWoS, HBM2e, HBM3, interposer, subscriber only (general), TSMC

TSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.

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Architectures Manycore Processors 

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI

July 10, 2021August 2, 2021 David Schor 7 nm, Esperanto, ET-Maxion, ET-Minion, ET-SoC-1, neural processors, RISC-V, TSMC

A look at Esperanto’s ET-SoC-1, the startup’s first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.

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Foundries Process Technologies Roadmaps Subscriber Only Content 

TSMC 2021 Foundry Update: Foundry Roadmap

July 6, 2021July 6, 2021 David Schor 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N2 2 nm, N3, N4, N5, N6, N7, subscriber only (general), TSMC

TSMC 2021 foundry update

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Foundries 

Q1 2021 Foundry Update: Spending Bonanza

May 18, 2021May 23, 2021 David Schor 10 nm, 3 nm, 5 nm, 7 nm, FinFET, GAA, Intel, Samsung, SMIC, TSMC

A look at the current state of leading-edge foundries for the first quarter of 2021.

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Foundries Roadmaps 

TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

May 14, 2020May 23, 2021 David Schor 5 nm, TSMC

TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.

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  • ← Previous

Top Six Articles

  • A Look At Intel 4 Process Technology
  • N3E Replaces N3; Comes In Many Flavors
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO
  • A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor
  • A Look at Cerebras Wafer-Scale Engine: Half Square Foot Silicon Chip

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Intel Launches Mainstream Cascade Lake Xeon W Workstation Processors

Intel Launches Mainstream Cascade Lake Xeon W Workstation Processors

October 7, 2019May 25, 2021 David Schor
IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

IBM Adds POWER9 AIO, Pushes for an Open Memory-Agnostic Interface

November 3, 2019May 25, 2021 David Schor
Cavium Takes ARM to Petascale with Astra

Cavium Takes ARM to Petascale with Astra

August 25, 2018May 25, 2021 David Schor
The RISC-V momentum continues with the GAP8, a new IoT/AI Application Processor

The RISC-V momentum continues with the GAP8, a new IoT/AI Application Processor

February 28, 2018May 25, 2021 David Schor
Intel Pushes Out Flagship Premium Tiger Lake Mobile Chips

Intel Pushes Out Flagship Premium Tiger Lake Mobile Chips

May 13, 2021May 23, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

ASML Starts NXE:3400C Shipment, But Supply Constraints Loom

ASML Starts NXE:3400C Shipment, But Supply Constraints Loom

October 17, 2019May 25, 2021 David Schor
Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

Hot Chips 33 Program: Alder Lake, Sapphire Rapids, Zen 3, Next-Gen Z, Neoverse N2, And Many More

May 13, 2021May 23, 2021 David Schor
Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen

May 3, 2019May 25, 2021 David Schor
IBM Introduces Next-Gen Z  Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

September 14, 2019May 25, 2021 David Schor
DARPA ERI: HIVE and Intel PUMA Graph Processor

DARPA ERI: HIVE and Intel PUMA Graph Processor

August 4, 2019May 25, 2021 David Schor
Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

Inside Rosetta: The Engine Behind Cray’s Slingshot Exascale-Era Interconnect

February 9, 2020May 25, 2021 David Schor
TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

May 14, 2020May 23, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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