TSMC – WikiChip Fuse

Foundries Process Technologies Roadmaps

TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node

October 26, 2021October 26, 2021 David Schor 5 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N4, N4P, N5, TSMC

TSMC introduces a new 5-nanometer derivative – an enhanced performance N4P node.

Architectures Server Processors

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor 5 nm, Alibaba, Apsara Conference 2021, ARM, ARMv9, Panjiu, RISC-V, T-Head, TSMC, Xuantie, Yitian 710

Alibaba open-source its high-performance XuanTie RISC-V Cores; introduces a new in-house Armv9 server chip

Packaging Subscriber Only Content

5th Gen CoWoS-S Extends 3 Reticle Size

August 2, 2021August 2, 2021 David Schor 2.5D packaging, CoWoS, HBM2e, HBM3, interposer, subscriber only (general), TSMC

TSMC’s 5th Generation CoWoS-S Extends 3 Reticle Size.

Architectures Manycore Processors

A Look At The ET-SoC-1, Esperanto’s Massively Multi-Core RISC-V Approach To AI

July 10, 2021August 2, 2021 David Schor 7 nm, Esperanto, ET-Maxion, ET-Minion, ET-SoC-1, neural processors, RISC-V, TSMC

A look at Esperanto’s ET-SoC-1, the startup’s first AI inference accelerator for the data center. The company took a unique RISC-V approach with a massively multi-core chip with nearly 1,100 custom-designed CPU cores.

Foundries Process Technologies Roadmaps Subscriber Only Content

TSMC 2021 Foundry Update: Foundry Roadmap

July 6, 2021July 6, 2021 David Schor 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, Extreme Ultraviolet (EUV) Lithography, FinFET, N2 2 nm, N3, N4, N5, N6, N7, subscriber only (general), TSMC

TSMC 2021 foundry update

Q1 2021 Foundry Update: Spending Bonanza

May 18, 2021May 23, 2021 David Schor 10 nm, 3 nm, 5 nm, 7 nm, FinFET, GAA, Intel, Samsung, SMIC, TSMC

A look at the current state of leading-edge foundries for the first quarter of 2021.

Foundries Roadmaps

TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

May 14, 2020May 23, 2021 David Schor 5 nm, TSMC

TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.

Foundries Process Technologies Roadmaps

TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

April 17, 2020May 25, 2021 David Schor 3 nm, 5 nm, FinFET, N3, N5, N5P, N7, N7P, TSMC

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020May 25, 2021 David Schor 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

Architectures Floorplanning Interconnects ISSCC 2020

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

February 21, 2020May 25, 2021 David Schor 14 nm, 7 nm, AMD, capacitance, GlobalFoundries, ISSCC, ISSCC 2020, resistance, TSMC, wire delay, Zen, Zen 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

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