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TSMC To Build A 5-Nanometer Fab In Arizona; Invest $12B Over The Next 8 Years

TSMC announces its intention to build and operate an advanced 5-nanometer fab in Arizona.

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TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

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TSMC Details 5 nm

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

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7nm Boosted Zen 2 Capabilities but Doubled the Challenges

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.

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TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

7-nanometer contributes the lion’s share of wafer revenue to TSMC’s fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

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TSMC Digs Trenches In Search Of Higher Performance

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

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TSMC 5-Nanometer Update

An update on TSMC’s upcoming 5-nanometer process technology.

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TSMC N7+ EUV Process Starts Shipping

TSMC announces its N7+ process which entered HVM earlier this year is now shipping products to market.

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TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

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