TSMC – WikiChip Fuse

TSMC N7+ EUV Process Starts Shipping

David SchorProcess TechnologiesOctober 7, 2019 Tagged 7nm, EUV, N6, N7, TSMC

TSMC announces its N7+ process which entered HVM earlier this year is now shipping products to market.

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

David SchorPackaging, Process Technologies, SEMICON West 2019, VLSI 2019July 28, 2019 Tagged 3D packaging, 3nm, 5nm, 6nm, 7nm, CoWoS, InFO, InFO_AiP, InFO_MS, InFO_oS, N5, N5P, N6, N7, N7P, SemiConWest, SoIC, TSMC, VLSI 2019, VLSI Symposium

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

David SchorInterconnects, Packaging, Server Processors, VLSI 2019June 22, 2019 Tagged 7nm, ARM, ARMv8, chiplet, Cortex-A72, CoWoS, LIPINCON, TSMC, VLSI 2019, VLSI Symposium

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

David SchorProcess Technologies, VLSI 2019June 16, 2019 Tagged 7HPC, 7nm, FinFET, SDM845, SDM855, Snapdragon 800, Snapdragon 855, TSMC, VLSI 2019, VLSI Symposium

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

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TSMC Announces 6-Nanometer Process

David SchorProcess TechnologiesApril 16, 2019 Tagged 6 nm, EUV, TSMC

TSMC announces the 6-nanometer process, an enhanced 7 nm EUV node.

TSMC Starts 5-Nanometer Risk Production

David SchorProcess TechnologiesApril 6, 2019 Tagged 5 nm, 7 nm, FinFET, risk production, TSMC

TSMC 5-nanometer node has entered risk production with PDKs available for production design. Here’s is our initial density estimates.

QUEST, A TCI-Based 3D-Stacked SRAM Neural Processor

David SchorArchitectures, Circuit Design, ISSCC 2018, Neural ProcessorsApril 25, 2018 Tagged 3D packaging, 40 nm, 40LP, AI, die stacking, Hokkaido University, ISSCC, ISSCC 2018, Keio University, process technology, TCI, ThruChip Interface, TSMC, TSV

Attempting to address the memory bandwidth problem, the QUEST neural processor uses 3D-stacked SRAM dies along with ThruChip Interface wireless communication technology to deliver sufficiently high bandwidth to sustain peak processing performance.

The RISC-V momentum continues with the GAP8, a new IoT/AI Application Processor

David SchorEmbedded Processors, Neural ProcessorsFebruary 28, 2018 Tagged 55LP, 55nm, AI, Deep Learning, edge computing, GreenWaves, IoT, RISC-V, TSMC

The RISC-V momentum continues with the the launch of the GAP8, an IoT/AI ultra-low power application processor by GreenWaves, a France-based startup. The chip is designed for lengthy autonomous battery-powered edge/IoT inference operations.

Zhaoxin launches their highest-performance Chinese x86 chips

David SchorDesktop Processors, Mobile Processors, Server ProcessorsJanuary 21, 2018 Tagged 28nm, China, HLMC, KaisHeng, KaiXian, TSMC, VIA Technologies, x86, Zhaoxin

Zhaoxin has launched the highest-performance domestic Chinese x86 chips based on the WuDaoKou microarchitecture. Zhaoxin new chips are a brand new SoC design featuring higher performance cores, a new DDR4 memory controller and integrated graphics.

Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster

David SchorManycore Processors, Neural ProcessorsJanuary 1, 2018 Tagged 7nm, AI, Esperanto, HBM, RISC-V, TSMC

Exiting stealth mode, Esperanto, a small start-up lead by Dave Ditzel has unveiled their high-performance RISC-V cores they have been working on. Their first product will be a 4,096-core manycore processor designed for accelerating AI workloads.