TSMC Demos SoIC_H for High-Bandwidth HPC Applications
Today, by far, the most common packaging technology of choice for HPC applications that feature intensive memory bandwidths is the Chip-on-Wafer-on-Substrate (CoWoS) package. This versatile packaging option has grown quite extensively from its humble beginning in applications such as the Xilinx 7V200T and AMD Fiji. As CoWoS capabilities grew, and so did the supported packaging size and dies, so did parasitics' impact at the system level. With the most recent advanced nodes, the impact of the packaging interconnects has gotten noticeably worse,
This article is reserved for our subscribers.
In addition to our usual, free, coverage of cutting-edge semiconductor technologies and state-of-art chips, a subscription offers exclusive, early access to additional articles such as this one. Learn more here.
