HPC – WikiChip Fuse

TSMC Demos SoIC_H for High-Bandwidth HPC Applications

October 4, 2022October 4, 2022 David Schor 2.5D packaging, 3D packaging, HPC, hybrid bonding, SoIC, SoIC_H, SRAM cube, subscriber only (general), TSMC

[Subscription] TSMC demonstrates SoIC_H for next-generation high-bandwidth HPC applications.

Foundries Process Technologies Roadmaps Subscriber Only Content

TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

July 6, 2021July 6, 2021 David Schor 5 nm, 7 nm, HPC, N5A, N5HPC, N6RF, N7HPC, subscriber only (general)

A TSMC 2021 foundry update: automotive, networking, and HPC roadmap.

Foundries Interconnects Packaging Process Technologies

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

May 11, 2019May 25, 2021 David Schor 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Supercomputers

Cavium Takes ARM to Petascale with Astra

August 25, 2018May 25, 2021 David Schor ARM, ARMv8, Cavium, DoE, HPC, Marvell, Sandia, Supercomputers, ThunderX, ThunderX2, Vulcan

A look at the Astra supercomputer, the most powerful ARM-based supercomputer being built for Sandia National Labs.

Server Processors Supercomputers

A Look at Cavium’s New High-Performance ARM Microprocessors and the Isambard Supercomputer

June 3, 2018May 25, 2021 David Schor 16nm, ARM, ARMv8, Cavium, HPC, Marvell, ThunderX, ThunderX2, Vulcan

Reaching general availability, here is a look at Cavium’s new ThunderX2 family of high-performance ARM microprocessors for the data center.