Skip to content
Sunday, March 26, 2023
Latest:
  • A Look At AMD’s 3D-Stacked V-Cache
  • IEDM 2022: Did We Just Witness The Death Of SRAM?
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

N7HPC

Foundries Process Technologies Roadmaps Subscriber Only Content 

TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

July 6, 2021July 6, 2021 David Schor 5 nm, 7 nm, HPC, N5A, N5HPC, N6RF, N7HPC, subscriber only (general)

A TSMC 2021 foundry update: automotive, networking, and HPC roadmap.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • TSMC Extends Its 5nm Family With A New Enhanced-Performance N4P Node
  • Arm Introduces The Cortex-A715
  • Arm Introduces Its Confidential Compute Architecture
  • Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips
  • AMD’s Zen CPU Complex, Cache, and SMU

Recent

  • A Look At AMD’s 3D-Stacked V-Cache

    A Look At AMD’s 3D-Stacked V-Cache

    December 27, 2022December 27, 2022 David Schor
  • IEDM 2022: Did We Just Witness The Death Of SRAM?

    IEDM 2022: Did We Just Witness The Death Of SRAM?

    December 14, 2022December 15, 2022 David Schor
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance  RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor

Random Picks

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor
Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

October 1, 2022October 3, 2022 David Schor
Samsung 2nd gen 10nm enters HVM, S3 fab ready for primetime

Samsung 2nd gen 10nm enters HVM, S3 fab ready for primetime

November 29, 2017May 25, 2021 David Schor
Arm Introduces The Cortex-A715

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Intel launches Gemini Lake

Intel launches Gemini Lake

December 11, 2017May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

GlobalFoundries, Arm Demonstrate High-Density 3D Stacked Mesh Interconnect for HPC Applications

September 21, 2019June 11, 2021 David Schor
Qualcomm Refreshes Mid-Range Lines with the 632, 439, and 429

Qualcomm Refreshes Mid-Range Lines with the 632, 439, and 429

June 27, 2018May 25, 2021 David Schor
Nantero’s NRAM, A Universal Memory Candidate?

Nantero’s NRAM, A Universal Memory Candidate?

September 22, 2018May 25, 2021 David Schor
EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

EUV State, NXE:3600D, and Pellicle Readiness and Industrialization

November 20, 2021November 20, 2021 David Schor
Intel Announces a 5 GHz Core i7-8086K, Launches on the 40th Anniversary of the 8086

Intel Announces a 5 GHz Core i7-8086K, Launches on the 40th Anniversary of the 8086

June 5, 2018May 25, 2021 David Schor
SiFive Launches 7 Series, Their Highest Performance RISC-V Cores

SiFive Launches 7 Series, Their Highest Performance RISC-V Cores

November 8, 2018May 25, 2021 David Schor
A Look At AMD’s 3D-Stacked V-Cache

A Look At AMD’s 3D-Stacked V-Cache

December 27, 2022December 27, 2022 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2023 WikiChip LLC. All rights reserved.