Skip to content
Sunday, December 4, 2022
Latest:
  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency
  • The NPU Inside Every Intel PC
WikiChip Fuse

WikiChip Fuse

Your Chips and Semi News

  • Home
  • Account
  • Main Site
  • Architectures
    • x86
    • ARM
    • RISC-V
    • Power ISA
    • MIPS
  • Supercomputers
  • 14 nm
  • 12nm
  • 10nm
  • 7nm
  • 5nm

N7HPC

Foundries Process Technologies Roadmaps Subscriber Only Content 

TSMC 2021 Foundry Update: Automotive, Networking, and HPC Roadmap

July 6, 2021July 6, 2021 David Schor 5 nm, 7 nm, HPC, N5A, N5HPC, N6RF, N7HPC, subscriber only (general)

A TSMC 2021 foundry update: automotive, networking, and HPC roadmap.

Read more

Top Six Articles

  • A Look At Intel 4 Process Technology
  • N3E Replaces N3; Comes In Many Flavors
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process
  • A Look At Samsung’s 4LPE Process
  • Intel Rolls Out Next-Gen Data Center Portfolio; 100 Gigabit Ethernet, Optane DC, Hewitt Lake, and Cascade Lake With Up to 56 Cores
  • The Mesh Network For Next-Generation Neoverse Chips

Recent

  • SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    SiFive Announces New Cores, BiFurcates Line Into Performance And Efficiency Cores

    November 1, 2022November 2, 2022 David Schor
  • Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

    October 7, 2022October 7, 2022 David Schor
  • TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    TSMC Demos SoIC_H for High-Bandwidth HPC Applications

    October 4, 2022October 4, 2022 David Schor
  • Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    Intel Rolls Out 13th Gen Core, Raptor Lake Processors; Cranks Up The Frequency

    October 1, 2022October 3, 2022 David Schor
  • The NPU Inside Every Intel PC

    The NPU Inside Every Intel PC

    September 30, 2022September 30, 2022 David Schor
  • SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    SiFive Introduces A New Coprocessor Interface, Targets Custom Accelerators

    September 20, 2022September 20, 2022 David Schor

Random Picks

Intel Launches 10th Gen Comet Lake Desktop Processors

Intel Launches 10th Gen Comet Lake Desktop Processors

April 30, 2020May 23, 2021 David Schor
Intel Silently Launches Cannon Lake

Intel Silently Launches Cannon Lake

May 15, 2018May 25, 2021 David Schor
AMD 3D Stacks SRAM Bumplessly

AMD 3D Stacks SRAM Bumplessly

June 7, 2021June 7, 2021 David Schor
A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020May 25, 2021 David Schor
Leaked Intel Server Roadmap Shows Sapphire Rapids With DDR5/PCIe 5.0 For 2021, Granite Rapids For 2022

Leaked Intel Server Roadmap Shows Sapphire Rapids With DDR5/PCIe 5.0 For 2021, Granite Rapids For 2022

May 21, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3 nm 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

A Look at Spring Crest: Intel Next-Generation DC Training Neural Processor

November 10, 2019May 25, 2021 David Schor
DARPA ERI: HIVE and Intel PUMA Graph Processor

DARPA ERI: HIVE and Intel PUMA Graph Processor

August 4, 2019May 25, 2021 David Schor
Reincarnating The 6502 Using Flexible TFT Tech For IoT

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

December 10, 2019May 25, 2021 David Schor
Samsung 5 nm and 4 nm Update

Samsung 5 nm and 4 nm Update

October 19, 2019May 25, 2021 David Schor
Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer

Inside PFN’s AI Processor And The World’s Most Power-Efficient Supercomputer

September 20, 2021September 20, 2021 David Schor
Intel’s Total Memory Encryption, a new x86 extension for full memory encryption

Intel’s Total Memory Encryption, a new x86 extension for full memory encryption

December 17, 2017May 25, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

About

WikiChip
WikiChip is an independent publisher based in New York. The WikiChip Fuse section publishes chips and semiconductor related news with our main site offering in-depth semiconductor resources and analysis.

WikiChip Links

  • Main Site
  • WikiChip Fuse
  • Newsletter
  • Main Site
  • WikiChip Fuse

Copyright © 2022 WikiChip LLC. All rights reserved.