10nm – WikiChip Fuse

Intel Introduces 10nm Agilex FPGAs; Customized Connectivity with HBM, DDR5, PCIe Gen 5, and 112G Transceivers

David SchorFPGAsApril 2, 2019 Tagged 10nm, 112G, Agilex, DDR5, Falcon Mesa, FPGA, Intel, PCIe 4.0, PCIe 5.0

Intel has introduced their next-generation flagship data center FPGAs based on their 10-nanometer process. Utilizing a chiplet-based architecture, the company hopes to better customize the product for customer’s demand while iterating faster on PHYs and other connectivity protocols.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

David SchorArchitectures, Desktop Processors, Roadmaps, Server ProcessorsDecember 23, 2018 Tagged 10nm, 7nm, AVX-512, Foveros, Golden Cove, Gracemont, Ice Lake, Palm Cove, Sunny Cove, Tremont, Willow Cove, x86

Last week Intel disclosed initial details of their next-generation core microarchitecture, Sunny Cove, which will make it into future Ice Lake client and server chips among other products.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

David SchorProcess Technologies, VLSI 2018July 1, 2018 Tagged 10LPE, 10LPP, 10nm, 8LPP, 8nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

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VLSI 2018: Samsung’s 11nm nodelet, 11LPP

David SchorProcess Technologies, VLSI 2018June 30, 2018 Tagged 10nm, 11LPP, 11nm, 14nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 11nm 11LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

VLSI 2018: Next Week’s Samsung and GlobalFoundries Papers

David SchorVLSI 2018June 17, 2018 Tagged 10nm, 14nm, 7nm, 8nm, FinFET, GlobalFoundries, Qualcomm, Samsung, VLSI 2018, VLSI Symposium

A preview of some of the process technology papers from next week’s VLSI Symposium.

A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium

David SchorCircuit Design, Process TechnologiesJune 15, 2018 Tagged 10nm, cobalt, Intel, Intel Custom Foundry, metallization stack, ruthenium, TechInsights

WikiChip takes another look at Intel’s 10-nanometer standard cell design and discusses TechInsights findings of the first 10nm-based chip, the i3-8121U.