10nm – WikiChip Fuse

Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow

David SchorArchitecturesMay 28, 2019 Tagged 10nm, Ice Lake, Sunny Cove, x86

Intel disclosed additional details about their upcoming Sunny Cove core, claiming a large improvement in single-thread performance.

Intel Announces 10th Gen Core Processors Based On 10nm Ice Lake, Now Shipping

David SchorArchitectures, Mobile ProcessorsMay 28, 2019 Tagged 10nm, Ice Lake, Sunny Cove, x86

Intel announces 10th Generation Core based on the 10nm Ice Lake Chips which are now shipping to OEMs.

Leaked Intel Server Roadmap Shows Sapphire Rapids With DDR5/PCIe 5.0 For 2021, Granite Rapids For 2022

David SchorRoadmapsMay 21, 2019 Tagged 10nm, 7nm, Cooper Lake, Granite Rapids, Ice Lake, Sapphire Rapids, x86

A leaked roadmap of Intel server processors reveals some new details about their next-generation Sapphire Rapids and Granite Rapids processors.

Ice Lake Brings A New CPU, GPU, IPU, and I/Os, To Follow By Tiger Lake Next Year

David SchorArchitectures, Floorplanning, Mobile ProcessorsMay 12, 2019 Tagged 10nm, 7nm, AVX-512, Gen11, Ice Lake, Sapphire Rapids, Tiger Lake

A look at Ice Lake mobile CPUs which bring a new CPU core, a new Gen11 GPU, and a new 4th Gen IPU as well the new roadmap detailed by Intel at their recent investor meeting which includes Xeon Sapphire Rapids CPUs and 7nm Xe Data Center GPGPUs for 2021.

Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021

David SchorFoundries, Interconnects, Packaging, Process TechnologiesMay 11, 2019 Tagged 10nm, 3D packaging, 7nm, EMIB, HPC, Lakefield

An outline of Intel’s process technology and packaging plans including their 10nm and 7nm nodes as discussed at the company’s recent investor meeting.

Intel Introduces 10nm Agilex FPGAs; Customized Connectivity with HBM, DDR5, PCIe Gen 5, and 112G Transceivers

David SchorFPGAsApril 2, 2019 Tagged 10nm, 112G, Agilex, DDR5, Falcon Mesa, FPGA, Intel, PCIe 4.0, PCIe 5.0

Intel has introduced their next-generation flagship data center FPGAs based on their 10-nanometer process. Utilizing a chiplet-based architecture, the company hopes to better customize the product for customer’s demand while iterating faster on PHYs and other connectivity protocols.

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips

David SchorArchitectures, Desktop Processors, Roadmaps, Server ProcessorsDecember 23, 2018 Tagged 10nm, 7nm, AVX-512, Foveros, Golden Cove, Gracemont, Ice Lake, Palm Cove, Sunny Cove, Tremont, Willow Cove, x86

Last week Intel disclosed initial details of their next-generation core microarchitecture, Sunny Cove, which will make it into future Ice Lake client and server chips among other products.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

David SchorInterconnects, Packaging, Process TechnologiesDecember 22, 2018 Tagged 10nm, 2.5D packaging, 3D packaging, 5nm, 7nm, EMIB, Foveros, heterogeneous integration, interconnects, interposer, Lakefield, multi-chip package, Packaging, x86

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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VLSI 2018: Samsung’s 8nm 8LPP, a 10nm extension

David SchorProcess Technologies, VLSI 2018July 1, 2018 Tagged 10LPE, 10LPP, 10nm, 8LPP, 8nm, FinFET, Samsung, VLSI 2018, VLSI Symposium

A look at Samsung’s 8nm 8LPP process that was recently disclosed at the 38th Symposium on VLSI Technology.

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