IEDM 2019

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

April 5, 2020 David Schor 1 Comment 10 nm, 22 nm, 22FFL, 3D packaging, Foveros, Intel, Lakefield, Sunny Cove, Tremont

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

Foundries IEDM 2019 ISSCC 2020 Process Technologies

TSMC Details 5 nm

March 21, 2020 David Schor 4 Comments 5 nm, 7 nm, EUV, N5, N5P, TSMC

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

IEDM 2019 Interconnects Packaging Process Technologies

TSMC Digs Trenches In Search Of Higher Performance

December 14, 2019 David Schor 0 Comments 2.5D packaging, CoWoS, DTC, IEDM, IEDM 2019, MiM, TSMC

TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs.

IEDM 2019 Process Technologies Roadmaps

Intel 2020s Process Technology Roadmap: 10nm+++, 3nm, 2nm, and 1.4nm for 2029

December 10, 2019 David Schor 1 Comment 1.4 nm, 10 nm, 10nm, 2 nm, 3 nm, 5 nm, 7 nm, Intel

Intel’s process technology roadmap reveals decade-out plans, including a future 10nm+++ node and even a 1.4nm node heading into 2029.