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TSMC Ramps 5nm, Discloses 3nm to Pack Over a Quarter-Billion Transistors Per Square Millimeter

TSMC reports a flat Q1 amid the COVID-19 pandemic, ramps its 5nm node with good yield and discloses key 3-nanometer (N3) details. N3 will be a full node jump over N5 and is expected to offer over a quarter-billion transistors per each millimeter square of silicon.

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TSMC Details 5 nm

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

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TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

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