ISSCC 2020

A Look at Intel Lakefield: A 3D-Stacked Single-ISA Heterogeneous Penta-Core SoC

Architectures Hot Chips 31 IEDM 2019 ISSCC 2020 April 5, 2020 1

A look at Lakefield, Intel’s new mobile-class heterogeneous penta-core SoC built using two dies 3D-stacked face-to-face using the company Foveros packaging technology.

TSMC Details 5 nm

Foundries IEDM 2019 ISSCC 2020 Process Technologies March 21, 2020 3

TSMC details its 5-nanometer node for mobile and HPC applications. The process features the industry’s highest density transistors with a high-mobility channel and highest-density SRAM cells.

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

Architectures Circuit Design ISSCC 2020 March 8, 2020 5

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

Architectures Circuit Design ISSCC 2020 Manycore Processors Server Processors March 1, 2020 0

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

Radeon RX 5700: Navi and the RDNA Architecture

Architectures Circuit Design Graphics Processors ISSCC 2020 February 23, 2020 1

A look at AMD’s Radeon RX 5700 GPU built on a 7-nanometer process based on the new Navi microarchitecture and RDNA graphics architecture.

7nm Boosted Zen 2 Capabilities but Doubled the Challenges

Architectures Floorplanning Interconnects ISSCC 2020 February 21, 2020 2

The transition to 7 nm greatly enhanced AMD silicon capabilities but introduced new drastic design challenges that required new place and route methodologies and wire engineering.