z/Architecture

IBM Doubles Its 14nm eDRAM Density, Adds Hundreds of Megabytes of Cache

March 8, 2020May 25, 2021 David Schor 14HP, cache, eDRAM, IBM, IBM Z, ISSCC, ISSCC 2020, z/Architecture, z14, z15

IBM doubles its 14-nanometer eDRAM density through physical design work, enabling the packing of hundreds of additional megabytes of cache on the latest z15 microprocessor and system controller.

Architectures Server Processors

IBM Introduces Next-Gen Z Mainframe: The z15; Wider Cores, More Cores, More Cache, Still 5.2 GHz

September 14, 2019May 25, 2021 David Schor 14 nm, 14HP, cache, eDRAM, IBM, z/Architecture, z15

IBM introduces its latest Z mainframe, the z15. Here’s a detailed look at the changes and enhancements that were made including the new system architecture and CPU microarchitecture.

Architectures Circuit Design Floorplanning ISSCC 2018 Server Processors

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

May 13, 2018May 25, 2021 David Schor 14 nm, 14HP, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.