floorplan

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

David SchorCircuit Design, Floorplanning, IEDM 2018, Process TechnologiesJanuary 6, 2019 Tagged 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

Pages: 1 2 3 4

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

Pages: 1 2 3

AMD’s Zen CPU Complex, Cache, and SMU

David SchorArchitectures, Circuit Design, ISSCC 2018April 18, 2018 Tagged 14LPP, 14nm, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

Pages: 1 2

ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 9, 2018 Tagged 14nm, floorplan, Intel, ISSCC, ISSCC 2018, Skylake, Skylake-SP, x86, Xeon Scalable

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

Pages: 1 2