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  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
  • Arm Unveils Next-Gen Flagship Core: Cortex-X3
  • Arm Introduces The Cortex-A715
  • GlobalWafers To Build A 1.2M WPM Factory In Sherman, Texas
  • A Look At Samsung’s 4LPE Process
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floorplan

Circuit Design Floorplanning IEDM 2018 Process Technologies 

IEDM 2018: Intel’s 10nm Standard Cell Library and Power Delivery

January 6, 2019May 25, 2021 David Schor 10nm, DTCO, floorplan, IEDM, IEDM 2018, place and route, power delivery, routing, standard cell

Presented at the 64th IEEE International Electron Devices Meeting (IEDM) in December, here’s a look at Intel’s 10-nanometer standard cell library and power delivery system.

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Architectures Circuit Design Floorplanning ISSCC 2018 Server Processors 

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

May 13, 2018May 25, 2021 David Schor 14 nm, 14HP, A-Bus, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, X-Bus, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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Architectures Circuit Design ISSCC 2018 

AMD’s Zen CPU Complex, Cache, and SMU

April 18, 2018May 25, 2021 David Schor 14 nm, 14LPP, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

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Architectures Circuit Design Floorplanning ISSCC 2018 

ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan

March 9, 2018May 25, 2021 David Schor 14 nm, floorplan, Intel, ISSCC, ISSCC 2018, Skylake, Skylake-SP, x86, Xeon Scalable

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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Top Six Articles

  • Arm Unveils Next-Gen Flagship Core: Cortex-X3
  • Arm Introduces The Cortex-A715
  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
  • A Look At Intel 4 Process Technology
  • A Look At Samsung’s 4LPE Process
  • GlobalWafers To Build A 1.2M WPM Factory In Sherman, Texas

Recent

  • Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

    Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

    June 28, 2022June 28, 2022 David Schor
  • Arm Unveils Next-Gen Flagship Core: Cortex-X3

    Arm Unveils Next-Gen Flagship Core: Cortex-X3

    June 28, 2022June 28, 2022 David Schor
  • Arm Introduces The Cortex-A715

    Arm Introduces The Cortex-A715

    June 28, 2022June 29, 2022 David Schor
  • GlobalWafers To Build A 1.2M WPM Factory In Sherman, Texas

    GlobalWafers To Build A 1.2M WPM Factory In Sherman, Texas

    June 27, 2022June 27, 2022 David Schor
  • A Look At Samsung’s 4LPE Process

    A Look At Samsung’s 4LPE Process

    June 26, 2022June 26, 2022 David Schor
  • A Look At Intel 4 Process Technology

    A Look At Intel 4 Process Technology

    June 19, 2022June 20, 2022 David Schor

Random Picks

Reincarnating The 6502 Using Flexible TFT Tech For IoT

Reincarnating The 6502 Using Flexible TFT Tech For IoT

May 8, 2022May 8, 2022 David Schor
Cavium Takes ARM to Petascale with Astra

Cavium Takes ARM to Petascale with Astra

August 25, 2018May 25, 2021 David Schor
X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor

February 5, 2018May 25, 2021 David Schor
ISSCC 2018: Intel’s Self-Powered Intelligent IoT Edge Mote

ISSCC 2018: Intel’s Self-Powered Intelligent IoT Edge Mote

April 2, 2018May 25, 2021 David Schor
TSMC Announces 6-Nanometer Process

TSMC Announces 6-Nanometer Process

April 16, 2019May 25, 2021 David Schor

Random Tags

2.5D packaging 3D packaging 5 nm 5nm 7 nm 7nm 10 nm 10nm 14 nm 16nm AI AMD ARM ARMv8 ARMv9 chiplet Coffee Lake Core i5 Core i7 Cortex edge computing EMIB EUV FinFET GlobalFoundries Hot Chips IBM Ice Lake IEDM inference Intel Intel 7 ISSCC multi-chip package neural processors process technology RISC-V Samsung subscriber only (general) Sunny Cove Supercomputers TSMC VLSI Symposium x86 Zen

x86 WorldView All

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling
Desktop Processors Mobile Processors 

Intel Introduces Thread Director For Heterogeneous Multi-Core Workload Scheduling

August 19, 2021August 19, 2021 David Schor

Intel introduces the Intel Thread Director for heterogeneous multi-core workload scheduling

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs
Architectures Server Processors 

Intel Unveils Sapphire Rapids: Next-Generation Server CPUs

August 19, 2021August 19, 2021 David Schor
Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance
Architectures Data Processing Unit Desktop Processors Mobile Processors 

Intel’s Gracemont Small Core Eclipses Last-Gen Big Core Performance

August 19, 2021August 21, 2021 David Schor
Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC
Architectures Desktop Processors Mobile Processors 

Intel Unveils Alder Lake: Next-Generation Mainstream Heterogeneous Multi-Core SoC

August 19, 2021August 19, 2021 David Schor
Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs
Architectures Desktop Processors Mobile Processors Server Processors 

Intel Details Golden Cove: Next-Generation Big Core For Client and Server SoCs

August 19, 2021August 19, 2021 David Schor
Intel Launches 3rd Gen Ice Lake Xeon Scalable
Architectures Server Processors 

Intel Launches 3rd Gen Ice Lake Xeon Scalable

April 6, 2021May 23, 2021 David Schor

Random

Forschungszentrum Jülich is upgrading its computing power

Forschungszentrum Jülich is upgrading its computing power

January 23, 2018May 25, 2021 Matt Larson
SEMICON West 2019: ASML EUV Update

SEMICON West 2019: ASML EUV Update

July 21, 2019May 25, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

March 1, 2020May 25, 2021 David Schor
The Mesh Network For Next-Generation Neoverse Chips

The Mesh Network For Next-Generation Neoverse Chips

May 22, 2021May 23, 2021 David Schor
DARPA ERI: HIVE and Intel PUMA Graph Processor

DARPA ERI: HIVE and Intel PUMA Graph Processor

August 4, 2019May 25, 2021 David Schor
Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

Arm Unveils Next-Gen Armv9 Little Core: Cortex-A510

May 25, 2021May 26, 2021 David Schor

ARM WorldView All

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency
Architectures Mobile Processors 

Arm Refreshes The Cortex-A510, Squeezes Higher Efficiency

June 28, 2022June 28, 2022 David Schor
Arm Unveils Next-Gen Flagship Core: Cortex-X3
Mobile Processors 

Arm Unveils Next-Gen Flagship Core: Cortex-X3

June 28, 2022June 28, 2022 David Schor
Arm Introduces The Cortex-A715
Architectures Mobile Processors 

Arm Introduces The Cortex-A715

June 28, 2022June 29, 2022 David Schor
Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip
Architectures Server Processors 

Alibaba Open Source XuanTie RISC-V Cores, Introduces In-House Armv9 Server Chip

October 20, 2021October 20, 2021 David Schor
Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration
Data Processing Unit 

Marvell Launches 5nm Octeon 10 DPUs with Neoverse N2 cores, AI Acceleration

June 28, 2021June 28, 2021 David Schor
Arm Introduces Its Confidential Compute Architecture
Architectures 

Arm Introduces Its Confidential Compute Architecture

June 23, 2021June 23, 2021 David Schor

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