floorplan

ISSCC 2018: The IBM z14 Microprocessor And System Control Design

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018, Server ProcessorsMay 13, 2018 Tagged 14HP, 14nm, floorplan, IBM, ISSCC, ISSCC 2018, mainframe, z/Architecture, z14

A look at the changes and enhancements that were implemented by IBM in their z14 mainframe microprocessor and system control chips.

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AMD’s Zen CPU Complex, Cache, and SMU

David SchorArchitectures, Circuit Design, ISSCC 2018April 18, 2018 Tagged 14LPP, 14nm, AMD, cache, floorplan, ISSCC, ISSCC 2017, ISSCC 2018, SRAM, x86, Zen

A look at AMD’s Zen CPU Complex (CCX), a fully independent and modular cluster of up to four cores that are incorporated into a full SoC to form complete products such as their Zeppelin die.

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ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan

David SchorArchitectures, Circuit Design, Floorplanning, ISSCC 2018March 9, 2018 Tagged 14nm, floorplan, Intel, ISSCC, ISSCC 2018, Skylake, Skylake-SP, x86, Xeon Scalable

At ISSCC 2018 Intel gave us some more interesting architectural details of their latest Skylake server microprocessors which brought a new mesh interconnect, a new cache hierarchy, and wider vector operations among a large array of other enhancements.

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