WikiChip Fuse
CEA-Leti Demos a 6-Chiplet 96-Core 3D-Stacked MIPS Processor

CEA-Leti demonstrates a high-performance microprocessor architecture with a 96-core MIPS processor built with six chiplets 3D-stacked on an active interposer die.

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Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

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