WikiChip Fuse
Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes

At the recent Intel Architecture Day, the company unveiled their latest advanced packaging technology called Foveros, a face-to-face three-dimensional (3D) die stacking packaging technology in an effort to assist with the slowing of Moore’s Law.

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A Look at NEC’s Latest Vector Processor, the SX-Aurora

A look at the NEC SX-Aurora, their latest vector processor – increasing compute while maintaining a high B/F through six HBM2 modules leveraging TSMC 2nd gen CoWoS technology. The SX-Aurora introduces a new form factor, system architecture, and execution model.

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Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem

Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.

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Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures

At the DARPA 2018 ERI Summit, Intel announced their contribution of a royalty-free bus standard to DARPA’s CHIPS Program, allowing seamless communication between multiple packaged chiplets.

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IEDM 2017: AMD’s grand vision for the future of HPC

Capping off a great year, AMD CEO Lisa Su opening address at IEDM 2017 highlighted key challenges for the future, predicting a paradigm shift in the design of processors and systems that will deliver another decade of performance gains.

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