3nm – WikiChip Fuse

TSMC Q4: 7nm Dominates Revenue, Preps 5nm Ramp, 6nm By EOY

January 17, 2020 David Schor 0 Comments 3nm, 5nm, 7nm, N3, N5, N6, N7, TSMC

7-nanometer contributes the lion’s share of wafer revenue to TSMC’s fourth-quarter driven by growth from smartphones and HPC. The foundry is also preparing the 5-nanometer node for early this year and the 6-nanometer by the end of the year.

Packaging Process Technologies SEMICON West 2019 VLSI 2019

TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging

July 28, 2019 David Schor 3 Comments 3D packaging, 3nm, 5nm, 6nm, 7nm, CoWoS, InFO, InFO_AiP, InFO_MS, InFO_oS, N5, N5P, N6, N7, N7P, SemiConWest, SoIC, TSMC, VLSI 2019, VLSI Symposium

An update on TSMC current and forthcoming logic process nodes as well as their next-generation advanced packaging technologies.

SEMICON West 2019

SEMICON West 2019: ASML EUV Update

July 21, 2019 David Schor 1 Comment 3nm, 5nm, 7nm, ASML, EUV, High-NA, NXE:3100, NXE:3300B, NXE:3400B

An update on the current state of EUV systems which was given by ASML at SEMICON West 2019 earlier this month.

ARM TechCon 2018 Foundries Packaging Process Technologies

Samsung 7nm Enters Risk Production, Talks Roadmap, Scaling Boosters, and the ARM Ecosystem

October 28, 2018 David Schor 3 Comments 2.5D packaging, 3D packaging, 3GAAE, 3GAAP, 3GAE, 3nm, 4LPE, 4LPP, 5LPE, 5nm, 7LPP, 7nm, EUV, Packaging, Samsung

Samsung gives an update on their 7nm EUV-based process, details the foundry technology roadmap down to 3nm and the ARM ecosystem that follows.